Patents by Inventor Jerome Marcelino

Jerome Marcelino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8320220
    Abstract: An energy assisted magnetic recording (EAMR) transducer coupled with a laser is described. The EAMR transducer has an air-bearing surface (ABS) residing near a media during use. The laser provides energy. The transducer includes a waveguide, a near field transducer (NFT) proximate to the ABS, a write pole, a heat spreader, and at least one coil. The waveguide directs the energy from the laser toward the ABS. The NFT is optically coupled with the waveguide, focuses the energy onto the media, and includes a disk having an NFT width. The write pole writes to the media. The heat spreader is thermally coupled with the NFT. A first portion of the heat spreader is between the NFT and the pole, is between the ABS and a second portion of the heat spreader, and has a first width. The second portion has a second width greater than the first width.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: November 27, 2012
    Assignee: Western Digital (Fremont), LLC
    Inventors: Hongxing Yuan, Wentao Yan, Shing Lee, Zhong Shi, Jerome Marcelino, Yunfei Li, Zhongyan Wang
  • Patent number: 6099699
    Abstract: A process for providing a thin encapsulation layer for thin film heads includes controlling the bias voltage of the substrate and head during the encapsulation layer deposition process. The bias voltage is first maintained at approximately 60 volts while the standard encapsulation overcoat portion of the layer is deposited. This may take approximately one hour. Over the next thirty minutes, the bias voltage is ramped from approximately 60 volts to approximately 200 volts in a gradual, linear manner to reduce the stress on the wafer and heads. The bias voltage is then maintained at approximately 200 volts for the next three hours while the remainder of the encapsulation layer is deposited. Because of the higher bias voltage, the layer is deposited in a substantially planar manner so that there is no need for a lapping back process. Stress to the head is minimized by ramping the bias voltage. In addition, relatively short studs can be used for routing signals to and from the read/write elements of the head.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: August 8, 2000
    Assignee: Matsushita-Kotobuki Electronics Industries, Ltd.
    Inventors: Wei Pan, Ann Kang, Jerome Marcelino