Abstract: A data collecting instrument including an input coupled with an output network port of a processing device, the input configured to receive a destination address of each data packet transmitted from the output network port, where the processing device is connected to a plurality of processing devices and is configured to transmit data packets from output network ports of the processing device to other devices of the plurality; one or more address registers configured to store information about a destination address range; a counter register configured to store a counter value; and digital circuitry coupled with the input, the one or more address registers, and the counter register; the digital circuitry configured to (i) determine, based on the information stored in the one or more address registers, that the destination address is within the destination address range; and (ii) increment the counter value stored in the counter register.

Abstract: Systems and techniques for network on a chip based computer architectures and communications therein are described. A described technique includes generating, at a first computing resource of a computer system, a chained packet sequence. A packet therein can specify a chain indicator to indicate inclusion in the chained packet sequence, a destination address, and an opcode. The technique includes routing the sequence to a second computing resource based on the destination address of a first chained packet in the sequence. The technique includes receiving the sequence at the second computing resource; performing the operation specified by the opcode of the first chained packet; and determining whether to process or forward one or more chained packets in a remainder portion of the sequence based on the destination address of a second chained packet of the sequence, the second chained packet being located at a beginning of the remainder portion.

Abstract: A computing system includes a plurality of computing resources that communicate with each other using network on a chip architecture. One of the plurality of computing resources is attached to memory external to the computing system through an external memory interface. The memory-attached computing resource is configured to read data from the memory and modify the read data prior to either writing the modified data back to the memory, or transmitting the modified data to one or more other of the computing resources, or both.

Abstract: Systems, devices, and techniques for routing packets are described. A described router includes ingress ports to receive packets; egress ports; ingress switch fabric coupled with the ingress ports; egress switch fabric coupled with the egress ports; floating buffers coupled between the ingress switch fabric and the egress switch fabric; and a controller. The controller can be configured to receive a packet via an ingress port, determine an egress port based on the packet's destination address, acquire a floating buffer, send to the egress port a buffer identifier corresponding to the acquired floating buffer, operate the ingress switch fabric to establish a first pathway between the acquired floating buffer and the ingress port to write the packet to the buffer, and operate the egress switch fabric to establish a second pathway between the acquired floating buffer and the egress port to write from the buffer to the egress port.

Abstract: In one aspect, a method implemented by a first sync controller includes receiving sync information, wherein the sync information (i) identifies a first sync process, (ii) indicates that the first sync controller is not a master controller of the first sync process, and (iii) identifies a group of components executing the first sync process, the group comprising a first processing device; receiving a first sync indication from the first processing device; storing an indication, associated with the first sync process, that the first sync indication was received from the first processing device; determining that a sync indication has been received from all components of the first group of components; and transmitting a second sync indication to a second sync controller.

Abstract: Systems, devices, and techniques for routing packets are described. A described router includes ingress ports to receive packets; egress ports; ingress switch fabric coupled with the ingress ports; egress switch fabric coupled with the egress ports; floating buffers coupled between the ingress switch fabric and the egress switch fabric; and a controller. The controller can be configured to receive a packet via an ingress port, determine an egress port based on the packet's destination address, acquire a floating buffer, send to the egress port a buffer identifier corresponding to the acquired floating buffer, operate the ingress switch fabric to establish a first pathway between the acquired floating buffer and the ingress port to write the packet to the buffer, and operate the egress switch fabric to establish a second pathway between the acquired floating buffer and the egress port to write from the buffer to the egress port.

Abstract: Systems and techniques for network on a chip based computer architectures and communications therein are described. A described technique includes generating, at a first computing resource of a computer system, a chained packet sequence. A packet therein can specify a chain indicator to indicate inclusion in the chained packet sequence, a destination address, and an opcode. The technique includes routing the sequence to a second computing resource based on the destination address of a first chained packet in the sequence. The technique includes receiving the sequence at the second computing resource; performing the operation specified by the opcode of the first chained packet; and determining whether to process or forward one or more chained packets in a remainder portion of the sequence based on the destination address of a second chained packet of the sequence, the second chained packet being located at a beginning of the remainder portion.

Abstract: In one aspect, a method implemented by a first sync controller includes receiving sync information, wherein the sync information (i) identifies a first sync process, (ii) indicates that the first sync controller is not a master controller of the first sync process, and (iii) identifies a group of components executing the first sync process, the group comprising a first processing device; receiving a first sync indication from the first processing device; storing an indication, associated with the first sync process, that the first sync indication was received from the first processing device; determining that a sync indication has been received from all components of the first group of components; and transmitting a second sync indication to a second sync controller.

Abstract: A computing system includes a plurality of computing resources that communicate with each other using network on a chip architecture. One of the plurality of computing resources is attached to memory external to the computing system through an external memory interface. The memory-attached computing resource is configured to read data from the memory and modify the read data prior to either writing the modified data back to the memory, or transmitting the modified data to one or more other of the computing resources, or both.

Abstract: A shared program memory and related components configured to distribute data from a memory block to multiple processors at the same time. An arbiter determines what processors are requesting data from the same memory locations. Data from that memory location is then accessed and sent to the requesting processors so that the data arrives at about the same time to each processor, for example, during the same clock cycle. Such distribution is made possible using a configuration such as a shared data bus with corresponding valid bits for each register or using a multicaster and separate data busses for each processor.

Abstract: A data collecting instrument including an input coupled with an output network port of a processing device, the input configured to receive a destination address of each data packet transmitted from the output network port, where the processing device is connected to a plurality of processing devices and is configured to transmit data packets from output network ports of the processing device to other devices of the plurality; one or more address registers configured to store information about a destination address range; a counter register configured to store a counter value; and digital circuitry coupled with the input, the one or more address registers, and the counter register; the digital circuitry configured to (i) determine, based on the information stored in the one or more address registers, that the destination address is within the destination address range; and (ii) increment the counter value stored in the counter register.

Abstract: A computer network may comprise a plurality of computing devices. In one example, a method may be provided for discovering topology of the computer network. The method may comprise sending, by a host computing device of the computing network, a neighbor discovery packet to each network interface of the host that has a connection, receiving a reply packet responding to the neighbor discovery packet, building a neighbor map for all neighbor computing devices to the host, sending a connection discovery packet to each network interface of the host that has a connection, receiving reply packets responding to the connection discovery packet, and building a connection map for connections among computing devices based on the information in the reply packets.

Abstract: A computer network may comprise a plurality of computing devices. In one example, a method may be provided for discovering topology of the computer network. The method may comprise sending, by a host computing device of the computing network, a neighbor discovery packet to each network interface of the host that has a connection, receiving a reply packet responding to the neighbor discovery packet, building a neighbor map for all neighbor computing devices to the host, sending a connection discovery packet to each network interface of the host that has a connection, receiving reply packets responding to the connection discovery packet, and building a connection map for connections among computing devices based on the information in the reply packets.