Abstract: A transient protection circuit (14) includes a resistor (22) having a first end adapted for connection to a first signal line (16) of a voltage supply (12) and a second opposite end connected to a voltage supply input (20) of an application circuit (18). In one embodiment, the resistor (22) defines an emitter (26) of a PNP transistor (24) having a floating base (28) and a collector (30) adapted for connection to a reference signal line (15) of the voltage supply (12). In an alternative embodiment (14′), the emitter (26) of the PNP transistor (24) is connected to the first end of the resistor (22). The transient protection circuit (14, 14′) is preferably formed on a monolithic integrated circuit including the application circuit (18) wherein a semiconductor layer (46) defining the first input to the resistor (22) also defines a bond pad (50).

Abstract: Circuitry for driving an electrical load (18) and regulating a load current (IL) therethrough includes a multiple output load driving device (20) having an input (26) receiving a gate drive signal (GD) thereat and operable to direct the load current (IL) therethrough from a collector (28) to main (22) and sense (24) outputs thereof. A control circuit is provided including an error amplifier (52) having a non-inverting input operable to receive a reference voltage and an inverting input operable to receive a sense voltage proportional to the portion of load current (IL) flowing through the sense output (24) of the load driving device (20), and producing an output based thereon to which a gate drive control circuit (54) is responsive to supply the gate drive signal (GD). A feedback capacitor (CFB) is disposed between the collector (28) of the load driving device (20) and a resistor string (R8, R9, RTRIM) establishing the reference voltage, and provides an AC coupling therebetween.

Abstract: A semiconductor power device (100) that includes active cells in an interior region of an epitaxial layer (16) on a semiconductor substrate (12), and an edge termination structure that surrounds the cells and separates the cells from the die edge (48). A polysilicon layer (26) overlies and is electrically insulated from the epitaxial layer (16), a gate metal field plate (36) contacts the polysilicon layer (26), and a portion of the polysilicon layer (26) forms a gate for each cell. Each of the active cells also has a collector/anode terminal formed by the substrate (12), an emitter/cathode terminal formed by a well (18), emitter diffusion (20) and emitter metal (22), and a base formed by the epitaxial layer (16).