Abstract: An integrated circuit having sense inputs for a sensed tip signal and a sensed ring signal of a subscriber loop is disclosed. The integrated circuit processes the sensed signals to generate an analog control signal for a subscriber loop linefeed driver. The linefeed driver does not reside within a same integrated circuit.

Abstract: An integrated circuit having sense inputs for a sensed tip signal and a sensed ring signal of a subscriber loop is disclosed. The integrated circuit processes the sensed signals to generate a control signal for a subscriber loop linefeed driver.

Abstract: A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.

Abstract: A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.

Abstract: Methods and apparatus for coupling outgoing analog audio signals to a subscriber line are described. One method includes the step of receiving the outgoing audio signal. The outgoing audio signal is coupled to the subscriber line through a plurality of transistors coupled in a common base configuration. In one embodiment, linefeed driver control signals for controlling battery feed to the subscriber line are received on the same signal lines as the outgoing audio signal. A subscriber line interface circuit apparatus includes a first circuit for coupling a received outgoing audio signal to a subscriber line. The first circuit couples the received outgoing audio signal to the subscriber line through a common base isolation stage. In various embodiments, the common base isolation stage comprises a plurality of bipolar junction transistors coupled in a common base configuration or a plurality of field effect transistors coupled in a common gate configuration.

Abstract: A technique for performing frequency margin testing of communications system circuit boards incorporates a frequency agile clock source on a communications system circuit board. The clock source may be programmed to operate the circuit board at a nominal operating frequency and at frequencies suitable to characterize actual and/or apparent frequency tolerances of the circuit board. The technique maintains transmission line integrity of the on-board clock.

Abstract: A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values.

Abstract: A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.

Abstract: A clock multiplier unit (CMU) used for a high speed communications system is supplied with an input reference clock and utilizes a narrowband phase-locked loop (PLL) to multiply the reference clock to supply a higher speed output clock used, e.g., as a FIFO read clock. The narrowband PLL sufficiently attenuates jitter in jitter frequencies of interest thereby allowing a relaxation of the jitter requirement for the input reference clock. The low speed clock used to write the FIFO may also be used as the reference clock. The bandwidth of the PLL may be selectable to accommodate reference clocks with different jitter specifications. The narrowband PLL transfer function may also be used to meet overall jitter transfer function requirements.

Abstract: An output buffer circuit drives multiple signal formats. The output buffer circuit reduces duplication of output bond pads on an integrated circuit die. The output buffer circuit reduces a need for including conversion buffers on system boards. A single integrated circuit including the output buffer circuit may meet a variety of applications. The output buffer achieves these results with a programmable output voltage swing and a programmable output common mode voltage. In some embodiments of the present invention, an integrated circuit includes at least one single-ended buffer and at least one differential circuit coupled to a pair of outputs. One of the single-ended buffer and the differential circuit is selectively enabled to provide a signal to the outputs.

Abstract: A subscriber line interface circuit apparatus includes a signal processor having sense inputs for sensed tip and ring signals of a subscriber loop. The signal processor generates linefeed driver control signals in response to the sensed signals. A linefeed driver provides the sensed tip and ring signals. The linefeed driver drives the subscriber loop in accordance with the linefeed driver control signals.

Abstract: A subscriber line interface circuit apparatus includes tip/ring sense circuitry generating a tip sense signal and a ring sense signal from three sensed currents, wherein the tip sense signal and the ring sense signal correspond to subscriber loop tip and ring currents, respectively. In one embodiment, the tip/ring sense circuitry includes a current mirror generating first and second mirrored sense currents from a first sense current proportional to a battery feed node voltage of a subscriber loop. Current differencing circuitry provides the tip sense signal from a difference between the first mirrored sense current and a second sense current associated with a tip line of the subscriber loop. The current differencing circuitry provides the ring sense signal from a difference between the second mirrored sense current and a third sense current associated with a ring line of the subscriber loop.

Abstract: A subscriber line interface apparatus includes a switching core generating a negative subscriber line battery supply voltage (VBAT) for supplying at least one of a tip line and a ring line of a subscriber line from a positive first supply voltage. The apparatus includes voltage control circuitry driving the switching core in accordance with a tracked signal corresponding to a sensed one of the tip and ring lines.

Abstract: A device is provided for use in, e.g., XO and VCXO applications that utilizes a terminal that can function in a first mode as a serial communications port and in a second mode as an output enable terminal controlling, for example, the clock output(s). In the first mode, the output enable function is unavailable through the terminal. After the terminal is programmed to operate in the second mode, the terminal functions permanently in the second mode.

Abstract: Subscriber line interface circuitry includes an integrated circuit having sense inputs for a sensed tip signal and a sensed ring signal of a subscriber loop. The integrated circuit generates a subscriber loop linefeed driver control signal in response to the sensed signals. In one embodiment, A linefeed driver includes power circuitry for providing battery feed to the ring and tip nodes of the subscriber loop in accordance with the linefeed control signal. The linefeed driver includes sense circuitry providing a sensed tip signal and a sensed ring signal. The sensed tip and ring signals correspond to a tip current and a ring current of the subscriber loop. In one embodiment, the integrated circuit is a complementary metal oxide semiconductor (CMOS) integrated circuit. In one embodiment, the linefeed driver comprises only discrete components.

Abstract: A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.