Patents by Inventor Jerrell P. Hein

Jerrell P. Hein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6104794
    Abstract: A communication system is provided which draws virtually no loop current during a ringing burst and only draws on-hook loop current during the caller ID field. More particularly, ringer burst circuitry may be powered from the user powered circuitry by the transmission of power across the isolation barrier rather than being powered from the phone line. Thus, loop current need not be drawn from the TIP/RING lines during ringer bursts. The isolation barrier may be a capacitive isolation barrier which allows bidirectional communication and extraction of power from signals transmitted across the barrier.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: August 15, 2000
    Assignee: Silicon Laboratories, Inc.
    Inventors: Jerrell P. Hein, Andrew W. Krone, Jeffrey W. Scott, Navdeep S. Sooch, David R. Welland
  • Patent number: 6078444
    Abstract: A circuit is provided for use with analog to digital conversion techniques in sampled amplitude read channel integrated circuits. A common ADC may be utilized for conversion of both high frequency disk data such as user data and servo data, for example, and for low frequency auxiliary data such as, for example, motor back-EMF current signals. The ADC may utilize the relatively low bit accuracy required for the read channel disk data and through oversampling techniques obtain sufficient conversion accuracy to meet the relatively higher precision requirements for the auxiliary data conversion. The auxiliary data is modified by a ramp signal and the ADC is run on a clock generated from a dithered frequency source so that ADC quantization errors may be randomized.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: June 20, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: G. Diwakar Vishakhadatta, David E. Reed, Jerrell P. Hein, G. Tyson Tuttle
  • Patent number: 6028727
    Abstract: A system and method is disclosed in which a circuit is provided to improve the settling performance of synthesizers used in read/write channel applications when the synthesizer is required to switch frequencies by a small percentage quickly. This is useful in read channel applications where the clock recovery is performed using an all-digital PLL. A digital timing recovery scheme is utilized in which one data frequency synthesizer provides both write and read frequencies. The read frequency is set higher than the write frequency to allow for oversampling when reading data from the storage medium. When changing from a write to read frequency or vice-versa the frequency synthesizer rapidly settles to the new frequency. The frequency synthesizer includes a phase locked loop which utilizes a controllable oscillator. The phase locked loop divisors are changed to obtain the desired frequency changes. An input signal to the controllable oscillator is also changed in order to obtain the rapid settling times.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: February 22, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: G. Diwakar Vishakhadatta, Jerrell P. Hein
  • Patent number: 5990814
    Abstract: A system and method for correcting comparator offsets which occur during operating conditions such that static and dynamic offsets are compensated is provided. The comparator may be calibrated for normal operating conditions. The calibration may be accomplished by providing adjustability of the comparators' threshold value and providing a feedback loop for adjusting the threshold value. In one preferred embodiment, the comparator may be utilized within a flash ADC, and in a more preferred embodiment, the comparator may be utilized within a flash ADC of a read/write channel circuit.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: November 23, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Russell Croman, Marius Goldenberg, Jerrell P. Hein
  • Patent number: 5986830
    Abstract: An improved write precompensation circuit for a read/write channel circuit and system is provided. Multiple data input signals are provided, each being clocked by a different clock. The data input signals are then multiplexed. Two, three or more data clock delays may be utilized to provide two, three or more data delays to achieve the write precompensation. Only one edge of a signal need pass through a multiplexer before the multiplexer may change state. The amount of delay may be user programmable.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: November 16, 1999
    Assignee: Cirrus Logic, Inc.
    Inventor: Jerrell P. Hein
  • Patent number: 5796535
    Abstract: A sampled amplitude read channel incorporated within a magnetic disk storage system for reading data recorded in concentric tracks on a magnetic medium, where the data comprises user data sectors recorded at varying data rates across a plurality of predefined zones and embedded servo data sectors recorded at the same data rate across the zones. The sampled amplitude read channel comprises a timing recovery component for synchronous sampling of a read signal from a magnetic read head positioned over the magnetic medium, a gain control component for adjusting the amplitude of the read signal, and a DC offset component for cancelling a DC offset in the read signal. These components are dynamically configured to operate according to whether the read channel is processing user data or embedded servo data.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: August 18, 1998
    Assignee: Cirrus Logic, Inc.
    Inventors: Tyson Tuttle, Diwakar Vishakhadatta, Jerrel P. Hein, David R. Welland, David E. Reed, Richard T. Behrens, William G. Bliss, Paul M. Romano, Trent O. Dudley, Christopher P. Zook
  • Patent number: 5150386
    Abstract: A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.
    Type: Grant
    Filed: February 9, 1989
    Date of Patent: September 22, 1992
    Assignee: Crystal Semiconductor Corporation
    Inventors: Kenneth J. Stern, Navdeep S. Sooch, Jerrell P. Hein
  • Patent number: 4902913
    Abstract: A novel analog comparator having cascaded gain stages powered by two buses, the voltages on which are dependent on a reference input voltage. A network, responsive to the reference input voltage, sets the voltages on the buses and isolates the buses from external power and ground to achieve high power supply and ground noise immunity. An alternative design of the network is provided which removes errors in the accuracy of the comparator resulting from differing drain-to-source voltages across the various transistors. The accuracy of the comparator is then dependent on the accuracy of matching predetermined ratios of the sizes of the transistors.
    Type: Grant
    Filed: July 1, 1988
    Date of Patent: February 20, 1990
    Assignee: American Telephone and Telegraph Company
    Inventors: Jerrell P. Hein, Thayamkulangara R. Viswanathan
  • Patent number: 4805198
    Abstract: A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.
    Type: Grant
    Filed: May 19, 1987
    Date of Patent: February 14, 1989
    Assignee: Crystal Semiconductor Corporation
    Inventors: Kenneth J. Stern, Navdeep S. Sooch, Jerrell P. Hein
  • Patent number: 4595874
    Abstract: A CMOS precision current source which is insensitive to changes in both ambient temperature and processing conditions. In particular, a CMOS circuit exhibits both a temperature dependent voltage (V(T)) and a temperature dependent on-chip resistance (R(T)) where the dependencies of both voltage and resistance are linear functions of temperature of the form y=mx+b. The ratio of the slopes (m.sub.V /m.sub.R) is constructed to be equal to the ratio of the y-intercepts (b.sub.v /b.sub.R), where this ratio is a constant value, denoted s. Therefore, since a constant output current I.sub.o is equal to V(T)/R(T), I.sub.o will be equal to the constant value s. Additionally, a constant reference voltage (V.sub.o) may also be provided with a minimal increase in the circuitry needed to provide the constant current.
    Type: Grant
    Filed: September 26, 1984
    Date of Patent: June 17, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Jerrell P. Hein, Navdeep S. Sooch