Patents by Inventor Jerrod Peterson

Jerrod Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963335
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a sandwich plate construction heatsink. The sandwich plate construction heatsink can include a cold plate, one or more heat pipes over the cold plate, and a top plate over the one or more heat pipes. The cold plate can include a channel to accommodate the one or more heat pipes and/or the top plate can include a channel to accommodate the one or more heat pipes. The cold plate can be over a heat source in the electronic device.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 16, 2024
    Assignee: Intel Corporation
    Inventors: Juha Tapani Paavola, Jerrod Peterson, Justin M. Huttula, Ellann Cohen, Ruander Cardenas
  • Patent number: 11679407
    Abstract: To address technical problems facing silicon transient thermal management, a thermal interface material (TIM) may be used to provide improved thermal conduction. The TIM may include a liquid metal (LM) TIM, which may provide a significant reduction in thermal resistance, such as a thermal resistance RTIM?0.01-0.025° C.-cm2/W. The LM TIM may be applied using a presoaked applicator, such as an open-cell polyurethane foam applicator that has been presoaked in a controlled amount of LM TIM. This LM presoaked applicator is then used to apply the LM TIM to one or more target thermal surfaces, thereby providing thermal and mechanical coupling between the LM TIM and the thermal surface. The resulting thermal surface and thermally conductive LM TIM may be used to improve thermal conduction for various silicon-based devices, including various high-power, high-performance system-on-chip (SoC) packages, such as may be used in portable consumer products.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Kyle Jordan Arrington, Joseph Blaine Petrini, Aaron McCann, Shankar Devasenathipathy, James Christopher Matayabas, Jr., Mostafa Aghazadeh, Jerrod Peterson
  • Patent number: 11616000
    Abstract: Methods and apparatus are disclosed to provide electrical shielding for integrated circuit packages using a thermal interface material. An integrated circuit package includes a substrate including a ground plane layer and a solder mask; a semiconductor die attached to the substrate, the solder mask layer separating the semiconductor die from the ground plane layer; and a thermal interface material surrounding at least a portion of the semiconductor die, the thermal interface material electrically coupled to the ground plane layer.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: March 28, 2023
    Assignee: Intel Corporation
    Inventors: Dong-Ho Han, Jaejin Lee, Jerrod Peterson, Kyle Arrington
  • Publication number: 20230022182
    Abstract: Thermal management systems having pre-stressed biasing elements and related methods are disclosed. An example electronic component includes a circuit board, a processor coupled to the circuit board, and a thermally conductive structure positioned adjacent the processor. The thermally conductive structure is to dissipate heat generated by the processor. The electronic component includes a pre-stressed biasing element coupled to the thermally conductive structure and positioned between the processor and the thermally conductive structure. The pre-stressed biasing element is pre-stressed prior to attachment to the thermally conductive structure and the circuit board.
    Type: Application
    Filed: March 31, 2022
    Publication date: January 26, 2023
    Inventors: Juha Paavola, Justin M. Huttula, Jerrod Peterson, Shawn McEuen, Kerry A. Stevens
  • Patent number: 11545410
    Abstract: Enhanced thermal energy transfer systems for semiconductor packages are provided. A thermally conductive member is disposed in the interstitial space between an upper surface of a semiconductor package and a lower surface of a thermal member. The thermally conductive member is disposed above a first portion of the upper surface of the semiconductor package having a relatively higher thermal energy output when the semiconductor package is operating. A thermal interface material is disposed in the interstitial space and a force applied to the thermal member. The thermally conductive member forms a relatively higher pressure region above the first portion of the semiconductor package and a relatively lower pressure region in other portions of the semiconductor package remote from the thermally conductive member. The increased pressure region proximate the thermally conductive member beneficially enhances the flow of thermal energy from the first portion of the semiconductor package to the thermal member.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: January 3, 2023
    Assignee: INTEL CORPORATION
    Inventors: Mark MacDonald, David Pidwerbecki, Mark Gallina, Jerrod Peterson
  • Patent number: 11251103
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to enable a segmented heatsink. The electronic device can include a printed circuit board, a substrate, where the substrate is over the printed circuit board, at least two heat sources over the substrate, and a segmented heatsink secured to the printed circuit board, where the segmented heatsink has at least two independent heatsink segments, where each heatsink segment corresponds to at least one heat source and is configured to draw heat from the corresponding heat source. In an example, the heat sources are at a different height.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Jerrod Peterson, Carin Lundquist Ruiz, Akhilesh P. Rallabandi
  • Publication number: 20210327782
    Abstract: Methods and apparatus are disclosed to provide electrical shielding for integrated circuit packages using a thermal interface material. An integrated circuit package includes a substrate including a ground plane layer and a solder mask; a semiconductor die attached to the substrate, the solder mask layer separating the semiconductor die from the ground plane layer; and a thermal interface material surrounding at least a portion of the semiconductor die, the thermal interface material electrically coupled to the ground plane layer.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 21, 2021
    Inventors: Dong-Ho Han, Jaejin Lee, Jerrod Peterson, Kyle Arrington
  • Patent number: 11081450
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, a radiation source on the substrate, a ground on the substrate, where the ground is located around the radiation source, and a heat spreader over the radiation source, where the heat spreader includes one or more ground coupling mechanisms that are in contact with the ground on the substrate. The one or more ground coupling mechanisms in contact with the ground on the substrate create a radiation shield that at least partially keeps radiation from the radiation source from extending past the substrate.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Dong-Ho Han, Jaejin Lee, Je-Young Chang, Jerrod Peterson, Mark Carbone
  • Publication number: 20210101175
    Abstract: To address technical problems facing silicon transient thermal management, a thermal interface material (TIM) may be used to provide improved thermal conduction. The TIM may include a liquid metal (LM) TIM, which may provide a significant reduction in thermal resistance, such as a thermal resistance RTIM?0.01-0.025 ° C.-cm2/W. The LM TIM may be applied using a presoaked applicator, such as an open-cell polyurethane foam applicator that has been presoaked in a controlled amount of LM TIM. This LM presoaked applicator is then used to apply the LM TIM to one or more target thermal surfaces, thereby providing thermal and mechanical coupling between the LM TIM and the thermal surface. The resulting thermal surface and thermally conductive LM TIM may be used to improve thermal conduction for various silicon-based devices, including various high-power, high-performance system-on-chip (SoC) packages, such as may be used in portable consumer products.
    Type: Application
    Filed: June 26, 2020
    Publication date: April 8, 2021
    Inventors: Kyle Jordan Arrington, Joseph Blaine Petrini, Aaron McCann, Shankar Devasenathipathy, James Christopher Matayabas, JR., Mostafa Aghazadeh, Jerrod Peterson
  • Patent number: 10880986
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to enable an active loading mechanism. The electronic device can include a printed circuit board, a heat source located on the printed circuit board, and an active loading mechanism secured to the printed circuit board. The active loading mechanism is over the heat source and includes shape memory material. When the shape memory material is not activated, the active loading mechanism applies a first load on the heat source and when the shape memory material is activated, the active loading mechanism applies a second load on the heat source.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Evan Piotr Kuklinski, Jerrod Peterson, Ruander Cardenas, Patrick Douglas James
  • Publication number: 20200337178
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a sandwich plate construction heatsink. The sandwich plate construction heatsink can include a cold plate, one or more heat pipes over the cold plate, and a top plate over the one or more heat pipes. The cold plate can include a channel to accommodate the one or more heat pipes and/or the top plate can include a channel to accommodate the one or more heat pipes. The cold plate can be over a heat source in the electronic device.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Juha Tapani Paavola, Jerrod Peterson, Justin M. Huttula, Ellann Cohen, Ruander Cardenas
  • Patent number: 10804168
    Abstract: Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon layer, where the thermal conductor includes one or more residual stresses. The thermal conductor is modified based on the one or more residual stress such that when pressure is applied to the thermal conductor, a profile of the thermal conductor at least approximately matches the profile of the silicon layer. In an example, the thermal conductor is modified by removing material from one or more areas of the thermal conductor and the thermal conductor is coupled to the silicon layer by one or more pressure inducing mechanisms.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Jerrod Peterson, David Pidwerbecki
  • Publication number: 20200027844
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, a radiation source on the substrate, a ground on the substrate, where the ground is located around the radiation source, and a heat spreader over the radiation source, where the heat spreader includes one or more ground coupling mechanisms that are in contact with the ground on the substrate. The one or more ground coupling mechanisms in contact with the ground on the substrate create a radiation shield that at least partially keeps radiation from the radiation source from extending past the substrate.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Applicant: Intel Corporation
    Inventors: Dong-Ho Han, Jaejin Lee, Je-Young Chang, Jerrod Peterson, Mark Carbone
  • Publication number: 20190371683
    Abstract: Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon layer, where the thermal conductor includes one or more residual stresses. The thermal conductor is modified based on the one or more residual stress such that when pressure is applied to the thermal conductor, a profile of the thermal conductor at least approximately matches the profile of the silicon layer. In an example, the thermal conductor is modified by removing material from one or more areas of the thermal conductor and the thermal conductor is coupled to the silicon layer by one or more pressure inducing mechanisms.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 5, 2019
    Applicant: Intel Corporation
    Inventors: Jerrod Peterson, David Pidwerbecki
  • Patent number: 10418291
    Abstract: Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon layer, where the thermal conductor includes one or more residual stresses. The thermal conductor is modified based on the one or more residual stress such that when pressure is applied to the thermal conductor, a profile of the thermal conductor at least approximately matches the profile of the silicon layer. In an example, the thermal conductor is modified by removing material from one or more areas of the thermal conductor and the thermal conductor is coupled to the silicon layer by one or more pressure inducing mechanisms.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Jerrod Peterson, David Pidwerbecki
  • Publication number: 20190252286
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to enable a segmented heatsink. The electronic device can include a printed circuit board, a substrate, where the substrate is over the printed circuit board, at least two heat sources over the substrate, and a segmented heatsink secured to the printed circuit board, where the segmented heatsink has at least two independent heatsink segments, where each heatsink segment corresponds to at least one heat source and is configured to draw heat from the corresponding heat source. In an example, the heat sources are at a different height.
    Type: Application
    Filed: March 29, 2019
    Publication date: August 15, 2019
    Applicant: INTEL CORPORATION
    Inventors: Jerrod Peterson, Carin Lundquist Ruiz, Akhilesh P. Rallabandi
  • Publication number: 20190246488
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to enable an active loading mechanism. The electronic device can include a printed circuit board, a heat source located on the printed circuit board, and an active loading mechanism secured to the printed circuit board. The active loading mechanism is over the heat source and includes shape memory material. When the shape memory material is not activated, the active loading mechanism applies a first load on the heat source and when the shape memory material is activated, the active loading mechanism applies a second load on the heat source.
    Type: Application
    Filed: March 29, 2019
    Publication date: August 8, 2019
    Applicant: Intel Corporation
    Inventors: Evan Piotr Kuklinski, Jerrod Peterson, Ruander Cardenas, Patrick Douglas James
  • Publication number: 20190139855
    Abstract: Enhanced thermal energy transfer systems for semiconductor packages are provided. A thermally conductive member is disposed in the interstitial space between an upper surface of a semiconductor package and a lower surface of a thermal member. The thermally conductive member is disposed above a first portion of the upper surface of the semiconductor package having a relatively higher thermal energy output when the semiconductor package is operating. A thermal interface material is disposed in the interstitial space and a force applied to the thermal member. The thermally conductive member forms a relatively higher pressure region above the first portion of the semiconductor package and a relatively lower pressure region in other portions of the semiconductor package remote from the thermally conductive member. The increased pressure region proximate the thermally conductive member beneficially enhances the flow of thermal energy from the first portion of the semiconductor package to the thermal member.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Applicant: Intel Corporation
    Inventors: Mark MacDonald, David Pidwerbecki, Mark Gallina, Jerrod Peterson
  • Publication number: 20190103326
    Abstract: Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon layer, where the thermal conductor includes one or more residual stresses. The thermal conductor is modified based on the one or more residual stress such that when pressure is applied to the thermal conductor, a profile of the thermal conductor at least approximately matches the profile of the silicon layer. In an example, the thermal conductor is modified by removing material from one or more areas of the thermal conductor and the thermal conductor is coupled to the silicon layer by one or more pressure inducing mechanisms.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: Intel Corporation
    Inventors: Jerrod Peterson, David Pidwerbecki
  • Publication number: 20190045658
    Abstract: Thermal exchanger securing devices, and compute resources that include one or more thermal exchanger securing devices, are disclosed herein. The thermal exchanger securing devices are used to secure a thermal exchanger to an integrated circuit package, and to secure a thermal exchanger and an integrated circuit package of a compute resource to a printed circuit board.
    Type: Application
    Filed: December 30, 2017
    Publication date: February 7, 2019
    Inventors: David Pidwerbecki, Jerrod Peterson, Christopher Moore