Patents by Inventor Jerrod Peterson
Jerrod Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11963335Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a sandwich plate construction heatsink. The sandwich plate construction heatsink can include a cold plate, one or more heat pipes over the cold plate, and a top plate over the one or more heat pipes. The cold plate can include a channel to accommodate the one or more heat pipes and/or the top plate can include a channel to accommodate the one or more heat pipes. The cold plate can be over a heat source in the electronic device.Type: GrantFiled: June 26, 2020Date of Patent: April 16, 2024Assignee: Intel CorporationInventors: Juha Tapani Paavola, Jerrod Peterson, Justin M. Huttula, Ellann Cohen, Ruander Cardenas
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Patent number: 11679407Abstract: To address technical problems facing silicon transient thermal management, a thermal interface material (TIM) may be used to provide improved thermal conduction. The TIM may include a liquid metal (LM) TIM, which may provide a significant reduction in thermal resistance, such as a thermal resistance RTIM?0.01-0.025° C.-cm2/W. The LM TIM may be applied using a presoaked applicator, such as an open-cell polyurethane foam applicator that has been presoaked in a controlled amount of LM TIM. This LM presoaked applicator is then used to apply the LM TIM to one or more target thermal surfaces, thereby providing thermal and mechanical coupling between the LM TIM and the thermal surface. The resulting thermal surface and thermally conductive LM TIM may be used to improve thermal conduction for various silicon-based devices, including various high-power, high-performance system-on-chip (SoC) packages, such as may be used in portable consumer products.Type: GrantFiled: June 26, 2020Date of Patent: June 20, 2023Assignee: Intel CorporationInventors: Kyle Jordan Arrington, Joseph Blaine Petrini, Aaron McCann, Shankar Devasenathipathy, James Christopher Matayabas, Jr., Mostafa Aghazadeh, Jerrod Peterson
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Patent number: 11616000Abstract: Methods and apparatus are disclosed to provide electrical shielding for integrated circuit packages using a thermal interface material. An integrated circuit package includes a substrate including a ground plane layer and a solder mask; a semiconductor die attached to the substrate, the solder mask layer separating the semiconductor die from the ground plane layer; and a thermal interface material surrounding at least a portion of the semiconductor die, the thermal interface material electrically coupled to the ground plane layer.Type: GrantFiled: June 25, 2021Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Dong-Ho Han, Jaejin Lee, Jerrod Peterson, Kyle Arrington
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Publication number: 20230022182Abstract: Thermal management systems having pre-stressed biasing elements and related methods are disclosed. An example electronic component includes a circuit board, a processor coupled to the circuit board, and a thermally conductive structure positioned adjacent the processor. The thermally conductive structure is to dissipate heat generated by the processor. The electronic component includes a pre-stressed biasing element coupled to the thermally conductive structure and positioned between the processor and the thermally conductive structure. The pre-stressed biasing element is pre-stressed prior to attachment to the thermally conductive structure and the circuit board.Type: ApplicationFiled: March 31, 2022Publication date: January 26, 2023Inventors: Juha Paavola, Justin M. Huttula, Jerrod Peterson, Shawn McEuen, Kerry A. Stevens
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Patent number: 11545410Abstract: Enhanced thermal energy transfer systems for semiconductor packages are provided. A thermally conductive member is disposed in the interstitial space between an upper surface of a semiconductor package and a lower surface of a thermal member. The thermally conductive member is disposed above a first portion of the upper surface of the semiconductor package having a relatively higher thermal energy output when the semiconductor package is operating. A thermal interface material is disposed in the interstitial space and a force applied to the thermal member. The thermally conductive member forms a relatively higher pressure region above the first portion of the semiconductor package and a relatively lower pressure region in other portions of the semiconductor package remote from the thermally conductive member. The increased pressure region proximate the thermally conductive member beneficially enhances the flow of thermal energy from the first portion of the semiconductor package to the thermal member.Type: GrantFiled: December 17, 2018Date of Patent: January 3, 2023Assignee: INTEL CORPORATIONInventors: Mark MacDonald, David Pidwerbecki, Mark Gallina, Jerrod Peterson
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Patent number: 11251103Abstract: Particular embodiments described herein provide for an electronic device that can be configured to enable a segmented heatsink. The electronic device can include a printed circuit board, a substrate, where the substrate is over the printed circuit board, at least two heat sources over the substrate, and a segmented heatsink secured to the printed circuit board, where the segmented heatsink has at least two independent heatsink segments, where each heatsink segment corresponds to at least one heat source and is configured to draw heat from the corresponding heat source. In an example, the heat sources are at a different height.Type: GrantFiled: March 29, 2019Date of Patent: February 15, 2022Assignee: Intel CorporationInventors: Jerrod Peterson, Carin Lundquist Ruiz, Akhilesh P. Rallabandi
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Publication number: 20210327782Abstract: Methods and apparatus are disclosed to provide electrical shielding for integrated circuit packages using a thermal interface material. An integrated circuit package includes a substrate including a ground plane layer and a solder mask; a semiconductor die attached to the substrate, the solder mask layer separating the semiconductor die from the ground plane layer; and a thermal interface material surrounding at least a portion of the semiconductor die, the thermal interface material electrically coupled to the ground plane layer.Type: ApplicationFiled: June 25, 2021Publication date: October 21, 2021Inventors: Dong-Ho Han, Jaejin Lee, Jerrod Peterson, Kyle Arrington
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Patent number: 11081450Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, a radiation source on the substrate, a ground on the substrate, where the ground is located around the radiation source, and a heat spreader over the radiation source, where the heat spreader includes one or more ground coupling mechanisms that are in contact with the ground on the substrate. The one or more ground coupling mechanisms in contact with the ground on the substrate create a radiation shield that at least partially keeps radiation from the radiation source from extending past the substrate.Type: GrantFiled: September 27, 2019Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Dong-Ho Han, Jaejin Lee, Je-Young Chang, Jerrod Peterson, Mark Carbone
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Publication number: 20210101175Abstract: To address technical problems facing silicon transient thermal management, a thermal interface material (TIM) may be used to provide improved thermal conduction. The TIM may include a liquid metal (LM) TIM, which may provide a significant reduction in thermal resistance, such as a thermal resistance RTIM?0.01-0.025 ° C.-cm2/W. The LM TIM may be applied using a presoaked applicator, such as an open-cell polyurethane foam applicator that has been presoaked in a controlled amount of LM TIM. This LM presoaked applicator is then used to apply the LM TIM to one or more target thermal surfaces, thereby providing thermal and mechanical coupling between the LM TIM and the thermal surface. The resulting thermal surface and thermally conductive LM TIM may be used to improve thermal conduction for various silicon-based devices, including various high-power, high-performance system-on-chip (SoC) packages, such as may be used in portable consumer products.Type: ApplicationFiled: June 26, 2020Publication date: April 8, 2021Inventors: Kyle Jordan Arrington, Joseph Blaine Petrini, Aaron McCann, Shankar Devasenathipathy, James Christopher Matayabas, JR., Mostafa Aghazadeh, Jerrod Peterson
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Patent number: 10880986Abstract: Particular embodiments described herein provide for an electronic device that can be configured to enable an active loading mechanism. The electronic device can include a printed circuit board, a heat source located on the printed circuit board, and an active loading mechanism secured to the printed circuit board. The active loading mechanism is over the heat source and includes shape memory material. When the shape memory material is not activated, the active loading mechanism applies a first load on the heat source and when the shape memory material is activated, the active loading mechanism applies a second load on the heat source.Type: GrantFiled: March 29, 2019Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: Evan Piotr Kuklinski, Jerrod Peterson, Ruander Cardenas, Patrick Douglas James
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Publication number: 20200337178Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a sandwich plate construction heatsink. The sandwich plate construction heatsink can include a cold plate, one or more heat pipes over the cold plate, and a top plate over the one or more heat pipes. The cold plate can include a channel to accommodate the one or more heat pipes and/or the top plate can include a channel to accommodate the one or more heat pipes. The cold plate can be over a heat source in the electronic device.Type: ApplicationFiled: June 26, 2020Publication date: October 22, 2020Applicant: Intel CorporationInventors: Juha Tapani Paavola, Jerrod Peterson, Justin M. Huttula, Ellann Cohen, Ruander Cardenas
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Patent number: 10804168Abstract: Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon layer, where the thermal conductor includes one or more residual stresses. The thermal conductor is modified based on the one or more residual stress such that when pressure is applied to the thermal conductor, a profile of the thermal conductor at least approximately matches the profile of the silicon layer. In an example, the thermal conductor is modified by removing material from one or more areas of the thermal conductor and the thermal conductor is coupled to the silicon layer by one or more pressure inducing mechanisms.Type: GrantFiled: August 19, 2019Date of Patent: October 13, 2020Assignee: Intel CorporationInventors: Jerrod Peterson, David Pidwerbecki
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Publication number: 20200027844Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, a radiation source on the substrate, a ground on the substrate, where the ground is located around the radiation source, and a heat spreader over the radiation source, where the heat spreader includes one or more ground coupling mechanisms that are in contact with the ground on the substrate. The one or more ground coupling mechanisms in contact with the ground on the substrate create a radiation shield that at least partially keeps radiation from the radiation source from extending past the substrate.Type: ApplicationFiled: September 27, 2019Publication date: January 23, 2020Applicant: Intel CorporationInventors: Dong-Ho Han, Jaejin Lee, Je-Young Chang, Jerrod Peterson, Mark Carbone
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Publication number: 20190371683Abstract: Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon layer, where the thermal conductor includes one or more residual stresses. The thermal conductor is modified based on the one or more residual stress such that when pressure is applied to the thermal conductor, a profile of the thermal conductor at least approximately matches the profile of the silicon layer. In an example, the thermal conductor is modified by removing material from one or more areas of the thermal conductor and the thermal conductor is coupled to the silicon layer by one or more pressure inducing mechanisms.Type: ApplicationFiled: August 19, 2019Publication date: December 5, 2019Applicant: Intel CorporationInventors: Jerrod Peterson, David Pidwerbecki
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Patent number: 10418291Abstract: Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon layer, where the thermal conductor includes one or more residual stresses. The thermal conductor is modified based on the one or more residual stress such that when pressure is applied to the thermal conductor, a profile of the thermal conductor at least approximately matches the profile of the silicon layer. In an example, the thermal conductor is modified by removing material from one or more areas of the thermal conductor and the thermal conductor is coupled to the silicon layer by one or more pressure inducing mechanisms.Type: GrantFiled: September 29, 2017Date of Patent: September 17, 2019Assignee: Intel CorporationInventors: Jerrod Peterson, David Pidwerbecki
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Publication number: 20190252286Abstract: Particular embodiments described herein provide for an electronic device that can be configured to enable a segmented heatsink. The electronic device can include a printed circuit board, a substrate, where the substrate is over the printed circuit board, at least two heat sources over the substrate, and a segmented heatsink secured to the printed circuit board, where the segmented heatsink has at least two independent heatsink segments, where each heatsink segment corresponds to at least one heat source and is configured to draw heat from the corresponding heat source. In an example, the heat sources are at a different height.Type: ApplicationFiled: March 29, 2019Publication date: August 15, 2019Applicant: INTEL CORPORATIONInventors: Jerrod Peterson, Carin Lundquist Ruiz, Akhilesh P. Rallabandi
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Publication number: 20190246488Abstract: Particular embodiments described herein provide for an electronic device that can be configured to enable an active loading mechanism. The electronic device can include a printed circuit board, a heat source located on the printed circuit board, and an active loading mechanism secured to the printed circuit board. The active loading mechanism is over the heat source and includes shape memory material. When the shape memory material is not activated, the active loading mechanism applies a first load on the heat source and when the shape memory material is activated, the active loading mechanism applies a second load on the heat source.Type: ApplicationFiled: March 29, 2019Publication date: August 8, 2019Applicant: Intel CorporationInventors: Evan Piotr Kuklinski, Jerrod Peterson, Ruander Cardenas, Patrick Douglas James
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Publication number: 20190139855Abstract: Enhanced thermal energy transfer systems for semiconductor packages are provided. A thermally conductive member is disposed in the interstitial space between an upper surface of a semiconductor package and a lower surface of a thermal member. The thermally conductive member is disposed above a first portion of the upper surface of the semiconductor package having a relatively higher thermal energy output when the semiconductor package is operating. A thermal interface material is disposed in the interstitial space and a force applied to the thermal member. The thermally conductive member forms a relatively higher pressure region above the first portion of the semiconductor package and a relatively lower pressure region in other portions of the semiconductor package remote from the thermally conductive member. The increased pressure region proximate the thermally conductive member beneficially enhances the flow of thermal energy from the first portion of the semiconductor package to the thermal member.Type: ApplicationFiled: December 17, 2018Publication date: May 9, 2019Applicant: Intel CorporationInventors: Mark MacDonald, David Pidwerbecki, Mark Gallina, Jerrod Peterson
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Publication number: 20190103326Abstract: Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon layer, where the thermal conductor includes one or more residual stresses. The thermal conductor is modified based on the one or more residual stress such that when pressure is applied to the thermal conductor, a profile of the thermal conductor at least approximately matches the profile of the silicon layer. In an example, the thermal conductor is modified by removing material from one or more areas of the thermal conductor and the thermal conductor is coupled to the silicon layer by one or more pressure inducing mechanisms.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Intel CorporationInventors: Jerrod Peterson, David Pidwerbecki
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Publication number: 20190045658Abstract: Thermal exchanger securing devices, and compute resources that include one or more thermal exchanger securing devices, are disclosed herein. The thermal exchanger securing devices are used to secure a thermal exchanger to an integrated circuit package, and to secure a thermal exchanger and an integrated circuit package of a compute resource to a printed circuit board.Type: ApplicationFiled: December 30, 2017Publication date: February 7, 2019Inventors: David Pidwerbecki, Jerrod Peterson, Christopher Moore