Abstract: A system and method for operating multiple security domains on one circuit card assembly, using a field-programmable gate array (FPGA) with an embedded security domain separation gate providing the MAC between multiple soft-core CPUs also embedded in the FPGA. In one embodiment, the FPGA is segregated into two or more security domains with no data paths between soft-core CPUs in each security domain except through the security domain separation gate. The security domain separation gate applies rules to any information to be transmitted between the security domains to avoid transmission of malicious content and to avoid transmission of information of a certain classification level or type to a security domain at a lower classification level or type.

Abstract: A system and method for operating multiple security domains on one circuit card assembly, using a field-programmable gate array (FPGA) with an embedded security domain separation gate providing the MAC between multiple soft-core CPUs also embedded in the FPGA. In one embodiment, the FPGA is segregated into two or more security domains with no data paths between soft-core CPUs in each security domain except through the security domain separation gate. The security domain separation gate applies rules to any information to be transmitted between the security domains to avoid transmission of malicious content and to avoid transmission of information of a certain classification level or type to a security domain at a lower classification level or type.

Abstract: Signal processing circuitry, preferably for use in multiplying two input signals, one at RF frequency and one at baseband frequency, which includes at least a basic four branch bridge circuit having a diode connected in each branch in a generally symmetrical four branch circuit configuration using a single bias supply and including a trimming resistor in at least one branch for controlling the current through the diodes in such branch so that the characteristics of the diodes in all branches can be matched over substantially the complete range of control current values therefor.

Abstract: Signal processing circuitry, preferably for use in multiplying two input signals, one at RF frequency and one at base-band frequency, which includes a pair of PIN diodes connected in a generally symmetrical circuit configuration using a single bias supply and including a trimming resistor for controlling the current through a selected one of the diodes so that the characteristics of both diodes can be matched over substantially the complete range of control current values therefor. Further, the circuit configuration permits the use of an easy and effective technique for compensating for temperature changes of the circuit during operation.

Abstract: An improved high speed digital communications diversity receiver using a forward adaptive transversal filter equalizer, having a plurality of weighting sections in each diversity channel to provide a combined weighting signal, wherein the required complex multiplications and correlations needed for weighting purposes are performed at IF frequencies, while the time-delayed combining operations for providing the desired combined weighted output signal are performed at baseband frequencies. Such an arrangement reduces the number of tapped delay lines normally needed for such transversal filter equalizer operation and further reduces the signal losses incurred in operating delay line devices at intermediate frequencies so that fewer large gain-bandwidth product amplifiers are required in the system than the number required in previously available systems using such forward transversal filter equalizers.