Abstract: A method is provided for detecting echo cancellation in a communication network. The method includes the steps of transmitting from an originating unit a pre-defined echo cancellation detection signal to a receiving unit. The resulting signal is detected by the receiving unit and analyzed to determine whether the differences between the resulting signal and a stored pre-defined signal indicate the detection of echo cancellation on the communication network.

Abstract: A method is provided for detecting echo cancellation in a communication network. The method includes the steps of transmitting from an originating unit a pre-defined echo cancellation detection signal to a receiving unit. The resulting signal is detected by the receiving unit and analyzed to determine whether the differences between the resulting signal and a stored pre-defined signal indicate the detection of echo cancellation on the communication network.

Abstract: A time slot interchange having a data channel memory, a channel circuit, having a write address output, the write address output connected to the data channel memory, a signal processing circuit, having a channel input coupled to the data channel memory, a gain input, and an output coupled to the time division multiplexed signal output port, and a connection memory, including a unique read channel field comprising a read address portion and a gain value portion for each data channel to be output by the time slot interchange network. The connection memory has an input connected to the write address output of the channel circuit, a read address output connected to the data channel memory, and a gain value output connected to the gain input of the signal processing circuit.

Abstract: A DRAM controller refreshers a DRAM having a maximum refresh interval. The DRAM controller measures a time interval after a refresh cycle, monitors a memory request input of the DRAM for an idle period after a measured time interval of substantially less than the maximum refresh interval, and refreshes the DRAM with a refresh cycle upon detecting one of an idle period and a measured time interval of the maximum refresh interval.