Patents by Inventor Jerry Chang-Jui Kao

Jerry Chang-Jui Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200410152
    Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.
    Type: Application
    Filed: September 15, 2020
    Publication date: December 31, 2020
    Inventors: CHIA HAO TU, HSUEH-CHIH CHOU, SANG HOO DHONG, JERRY CHANG JUI KAO, CHI-LIN LIU, CHENG-CHUNG LIN, SHANG-CHIH HSIEH
  • Patent number: 10867104
    Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a third type-one transistor, and a fourth type-one transistor. The first type-one transistor and the third type-one transistor are in the first portion of the type-one active zone. The integrated circuit includes a first type-two transistor in the first portion of the type-two active zone. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a gate configured to have the first supply voltage of a second power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 15, 2020
    Inventors: Chi-Yu Lu, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Jerry Chang Jui Kao, Yu-Ti Su, Wei-Hsiang Ma, Jiun-Jia Huang
  • Publication number: 20200350916
    Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
  • Patent number: 10824784
    Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia Hao Tu, Hsueh-Chih Chou, Sang Hoo Dhong, Jerry Chang Jui Kao, Chi-Lin Liu, Cheng-Chung Lin, Shang-Chih Hsieh
  • Publication number: 20200328202
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Po-Hsiang HUANG, Shao-Huan WANG, XinYong WANG, Yi-Kan CHENG, Chun-Chen CHEN
  • Publication number: 20200328212
    Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.
    Type: Application
    Filed: February 21, 2020
    Publication date: October 15, 2020
    Inventors: Guo-Huei WU, Jerry Chang Jui KAO, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jung-Chan YANG, Lee-Chung LU, Xiangdong CHEN
  • Publication number: 20200320244
    Abstract: An integrated circuit structure includes a first, a second and a third set of conductive structures and a first and a second set of vias. The first set of conductive structures extend in a first direction, and is located at a first level. The second set of conductive structures extends in a second direction, overlaps the first set of conductive structures, and is located at a second level. The first set of vias is between, and electrically couples the first and the second set of conductive structures. The third set of conductive structures extends in the first direction, overlaps the second set of conductive structures, covers a portion of the first set of conductive structures, and is located at a third level. The second set of vias is between, and electrically couples the second and the third set of conductive structures.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Jung-Chan YANG, Ting-Wei CHIANG, Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Lee-Chung LU, Li-Chun TIEN, Meng-Hung SHEN, Shang-Chih HSIEH, Chi-Yu LU
  • Publication number: 20200313659
    Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.
    Type: Application
    Filed: June 12, 2020
    Publication date: October 1, 2020
    Inventors: Ta-Pen GUO, Chi-Lin LIU, Shang-Chih HSIEH, Jerry Chang-Jui KAO, Li-Chun TIEN, Lee-Chung LU
  • Publication number: 20200285797
    Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • Publication number: 20200272778
    Abstract: A method includes: identifying ad hoc groups of elementary standard cells recurrent in a layout diagram, selecting one of the recurrent ad hoc groups (selected group) such that: the elementary standard cells in the selected group have connections representing a corresponding logic circuit; each elementary standard cell representing a logic gate; each ad hoc group has a number of transistors and a first number of logic gates; and the selected group providing a logical function. The method includes generating one or more macro standard cells such that: each macro standard cell has a number of transistors which is smaller than the number of transistors of the corresponding ad hoc group; or each macro standard cell has a second number of logic gates different than the first number of logic gates of the corresponding ad hoc group. The method also includes adding macro standard cells to the set of standard cells.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Inventors: Chi-Lin LIU, Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Lee-Chung LU, Shang-Chih HSIEH, Wei-Hsiang MA
  • Patent number: 10740531
    Abstract: An integrated circuit structure includes a set of gate structures, a first conductive structure, a first and second set of vias, and a first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the set of gate structures and is located at a second level. The first set of vias is between the set of gate structures and the first conductive structure. The first set of vias couple the set of gate structures to the first conductive structure. The first set of conductive structures extend in a second direction, overlap the first conductive structure, and is located at a third level. The second set of vias couple the first set of conductive structures to the first conductive structure, and is between the first set of conductive structures and the first conductive structure.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
  • Patent number: 10741539
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen
  • Patent number: 10735001
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Lun Ou, Jerry Chang Jui Kao, Lee-Chung Lu, Ruei-Wun Sun, Shang-Chih Hsieh, Ji-Yung Lin, Wei-Hsiang Ma, Yung-Chen Chien
  • Patent number: 10686428
    Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Pen Guo, Chi-Lin Liu, Shang-Chih Hsieh, Jerry Chang-Jui Kao, Li-Chun Tien, Lee-Chung Lu
  • Patent number: 10685162
    Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Patent number: 10664565
    Abstract: A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one ad hoc group amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Lee-Chung Lu, Shang-Chih Hsieh, Wei-Hsiang Ma
  • Publication number: 20200151297
    Abstract: A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.
    Type: Application
    Filed: July 25, 2019
    Publication date: May 14, 2020
    Inventors: JERRY CHANG JUI KAO, HUI-ZHONG ZHUANG, YUNG-CHEN CHIEN, TING-WEI CHIANG, CHIH-WEI CHANG, XIANGDONG CHEN
  • Publication number: 20200134130
    Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.
    Type: Application
    Filed: July 17, 2019
    Publication date: April 30, 2020
    Inventors: Cheok-Kei LEI, Jerry Chang Jui KAO, Chi-Lin LIU, Hui-Zhong ZHUANG, Zhe-Wei JIANG, Chien-Hsing LI
  • Publication number: 20200110912
    Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.
    Type: Application
    Filed: September 23, 2019
    Publication date: April 9, 2020
    Inventors: CHIA HAO TU, HSUEH-CHIH CHOU, SANG HOO DHONG, JERRY CHANG JUI KAO, CHI-LIN LIU, CHENG-CHUNG LIN, SHANG-CHIH HSIEH
  • Publication number: 20200099369
    Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Inventors: Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh, Che Min Huang