Abstract: Embodiments of the present invention generally provide apparatus and methods for supporting a gas distribution showerhead in a processing chamber. In one embodiment, a gas distribution showerhead for a vacuum chamber is provided. The gas distribution showerhead comprises a body having a first side and a second side opposite the first side, and a plurality of gas passages formed through the body, the gas passages comprising a first bore formed in the first side that is fluidly coupled to a second bore formed in the second side by a restricting orifice, and a suspension feature formed in the first bore of at least one of the gas passages.

Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a first gas mixture having a hydrogen containing gas to a silicon containing gas flow rate ratio greater than about 200:1 into the processing chamber, maintaining a first process pressure greater than about 6 Torr in the processing chamber to deposit a first microcrystalline silicon containing layer in presence of a plasma formed from the first gas mixture, supplying a second gas mixture into the processing chamber, and maintaining a second process pressure less than about 5 Torr in the processing chamber to deposit a second microcrystalline silicon containing layer in presence of a plasma formed from the second gas mixture.

Abstract: Embodiments of the present invention relate to methods for depositing an amorphous film that may be suitable for using in a NIP photodiode in display applications. In one embodiment, the method includes providing a substrate into a deposition chamber, supplying a gas mixture having a hydrogen gas to silane gas ratio by volume greater than 4 into the deposition chamber, maintaining a pressure of the gas mixture at greater than about 1 Torr in the deposition chamber, and forming an amorphous silicon film on the substrate in the presence of the gas mixture, wherein the amorphous silicon film is configured to be an intrinsic-type layer in a photodiode sensor.

Abstract: Excess flow valve devices, which are responsive to pressure and flow conditions in a bi-directional system, including structures to restrict flow in one direction through openings of a stopper of an excess flow valve based on balancing forces from at least a spring and a frictional force caused by the flow. Bi-directional system employing at least one pressure delayer responsive to pressure and flow impulses to protect a tank valve of a storage tank or a regulator during a refill phase or a discharge phase.

Abstract: A bi-directional pressurized system with devices for and configured to mitigate issues associated with leak and creep phenomena at various stages throughout the system, including valves and controls to distribute a leaked amount of fluid prior to delivery to a pressure-sensitive destination and a pressure relief valve to bring an initial pressure within an acceptable range for distribution to reach a target pressure. A startup method for mitigating leakage of the system during a rest phase, including selectively reducing the initial pressure upstream of a pressure-sensitive destination.

Abstract: An electrical connector (1), connected with a cable (5), comprises an insulative housing (2) having a plurality of cavities, a plurality of terminals (3) received in the cavities, and a latching member (4) attached to the housing. The latching member has a base plate (40) and a plurality of silos (44) extending from the base plate. A diameter of a channel (48) in each of the silos is slightly larger than a diameter of a corresponding wire (50) of the cable. During assembly of the connector and the cable, the wires of the cable extend through the channels of the latching member prior to connection of the terminals and the wires.

Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into the processing chamber, the gas mixture having a volumetric flow ratio of the hydrogen-based gas to the silicon-based gas greater than about 100:1, wherein a volumetric flow ratio of the argon gas to the total combined flow of hydrogen-based gas and the silicon-based gas is between about 5 percent and about 40 percent, and maintaining a process pressure of the gas mixture within the processing chamber at greater than about 3 Torr while depositing a microcrystalline silicon layer on the substrate.

Abstract: A physical vapor deposition target assembly is configured to isolate a target-bonding layer from a processing region. In one embodiment, the target assembly comprises a backing plate, a target having a first surface and a second surface, and a bonding layer disposed between the backing plate and the second surface. The first surface of the target is in fluid contact with a processing region and the second surface of the target is oriented toward the backing plate. The target assembly may include multiple targets.

Abstract: Methods and systems for generating and storing computer program execution trace data are disclosed. A method includes receiving a signal that enables the generation of computer program execution trace data in accordance with data stored in a register. The computer program execution trace data is generated and stored in memory.

Abstract: A method and apparatus having a RF return path with low impedance coupling a substrate support to a chamber wall in a plasma processing system is provided. In one embodiment, a processing chamber includes a chamber body having a chamber sidewall, a bottom and a lid assembly supported by the chamber sidewall defining a processing region, a substrate support disposed in the processing region of the chamber body, a shadow frame disposed on an edge of the substrate support assembly, and a RF return path having a first end coupled to the shadow frame and a second end coupled to the chamber sidewall.

Abstract: Embodiments of the present invention relate to methods for depositing an amorphous film that may be suitable for using in a NIP photodiode in display applications. In one embodiment, the method includes providing a substrate into a deposition chamber, supplying a gas mixture having a hydrogen gas to silane gas ratio by volume greater than 4 into the deposition chamber, maintaining a pressure of the gas mixture at greater than about 1 Torr in the deposition chamber, and forming an amorphous silicon film on the substrate in the presence of the gas mixture, wherein the amorphous silicon film is configured to be an intrinsic-type layer in a photodiode sensor.

Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into the processing chamber, the gas mixture having a volumetric flow ratio of the hydrogen-based gas to the silicon-based gas greater than about 100:1, wherein a volumetric flow ratio of the argon gas to the total combined flow of hydrogen-based gas and the silicon-based gas is between about 5 percent and about 40 percent, and maintaining a process pressure of the gas mixture within the processing chamber at greater than about 3 Torr while depositing a microcrystalline silicon layer on the substrate.

Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a first gas mixture having a hydrogen containing gas to a silicon containing gas flow rate ratio greater than about 200:1 into the processing chamber, maintaining a first process pressure greater than about 6 Torr in the processing chamber to deposit a first microcrystalline silicon containing layer in presence of a plasma formed from the first gas mixture, supplying a second gas mixture into the processing chamber, and maintaining a second process pressure less than about 5 Torr in the processing chamber to deposit a second microcrystalline silicon containing layer in presence of a plasma formed from the second gas mixture.

Abstract: The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting the semiconductor substrate with the high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen.

Abstract: The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting the semiconductor substrate with the high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen.

Abstract: A nickel silicon alloy barrier layer formed between a metal bonding pad on an integrated circuit and a tin-based solder ball, for example, a lead-free solder. The nickel silicon alloy contains at least 2 wt % silicon and preferably less than 20 wt %. An adhesion layer may be formed between the barrier layer and the bonding pad. For copper metallization, the adhesion layer may contain titanium or tantalum; for aluminum metallization, it may be aluminum. The nickel silicon alloy may be deposited by magnetron sputtering. Commercially available NiS4.5% sputter targets have provided a superior under-bump metallization (UBM) with lead-free tin solder bumps. Dopants other than silicon/may be used to reduce the magnetic permeability and provide other advantages of the invention.

Abstract: A wireless cursor indicating device includes a first body and a second body combined with each other. The first body includes a containing space for containing a control circuit and a wireless receiver, and ends of the first and second bodies include a positioning member and a wheel, and a latch is disposed between the first and second bodies, such that the first and second bodies can be turned with respect to each other by the fixing member and wheel to define a closed status when the first and second bodies are stacked with each other or an open status when the first and second bodies are disposed alternately with each other. The first and second bodies can be disposed alternately with each other by the effect of the latch, such that a containing space is exposed to facilitate users to access or storage objects in the containing space.

Abstract: A nickel silicon alloy barrier layer formed between a metal bonding pad on an integrated circuit and a tin-based solder ball, for example, a lead-free solder. The nickel silicon alloy contains at least 2 wt % silicon and preferably less than 20 wt %. An adhesion layer may be formed between the barrier layer and the bonding pad. For copper metallization, the adhesion layer may contain titanium or tantalum; for aluminum metallization, it may be aluminum. The nickel silicon alloy may be deposited by magnetron sputtering. Commercially available NiSi4.5% sputter targets have provided a superior under-bump metallization (UBM) with lead-free tin solder bumps. Dopants other than silicon/may be used to reduce the magnetic permeability and provide other advantages of the invention.

Abstract: A wireless cursor indicating device includes a first body and a second body combined with each other. The first body includes a containing space for containing a control circuit and a wireless receiver, and both sides of the first and second bodies include a sliding track and a sliding groove embedded with each other, and an elastic member and a limit member are embedded between the first and second bodies, so that the first and second bodies can be slid with respect to each other by means of the sliding track and sliding groove to define an OFF state or an ON state. With the operation of the elastic member and limit member, the first and second bodies in the ON state can be pulled by the elastic member without being disposed alternately, and only the containing space will be exposed for an easy access by users.

Abstract: A physical vapor deposition target assembly is configured to isolate a target-bonding layer from a processing region. In one embodiment, the target assembly comprises a backing plate, a target having a first surface and a second surface, and a bonding layer disposed between the backing plate and the second surface. The first surface of the target is in fluid contact with a processing region and the second surface of the target is oriented toward the backing plate. The target assembly may include multiple targets.