Abstract: A computing device and method are provided for converting unstructured data to structured data having a predetermined format. The computing device includes a memory storing unstructured data, an input device, a display, and a processor. The processor retrieves the unstructured data, loads parsing rules defining associations between properties of the unstructured data and the predetermined format, and applies the parsing rules to the unstructured data, dividing the unstructured data into sections. The sections contain portions of the unstructured data in fields defined by the predetermined format, and are presented on the display. A template is generated based on the sections, including, for each section, a record identifying the properties of the unstructured data contained in that section, and identifying corresponding fields of the predetermined format and values for those fields. The template is stored, and the sections are stored as structured data.

Abstract: Method, system, and programs for content search are disclosed. A user interface configured based on context information is presented within a host application. A plurality of selectable search results are then fetched based on the context information and a query received from a user through the user interface. An input associated with a selection of one or more selectable search results is received from the user through the user interface. The user interface is updated based on the plurality of selectable search results. In response to the selection, the one or more selected search results are provided to the host application with the context information.

Abstract: Method, system, and programs for displaying search results are disclosed. A first page that contains a first piece of content is presented to a user. A second page that contains a second piece of content including one or more search results is generated. The second page is arranged behind the first page such that the second page is invisible to the user. A first triggering event associated with a predetermined user input is detected. In response to the first triggering event, at least part of the first page is moved in a direction from a default position for a distance to expose at least part of the second page such that the second piece of content on the second page becomes visible to the user.

Abstract: Method, system, and programs for content search are disclosed. A user interface configured based on context information is presented within a host application. A plurality of selectable search results are then fetched based on the context information and a query received from a user through the user interface. An input associated with a selection of one or more selectable search results is received from the user through the user interface. The user interface is updated based on the plurality of selectable search results. In response to the selection, the one or more selected search results are provided to the host application with the context information.

Abstract: A search engine computer system is configured to produce an optimized display of maps especially useful in mobile handheld devices with comparatively small screens. The system factors in scoring functions, visibility, and empirical data on map levels to provide optimal map based results to users. This minimizes or avoids graphical results that overlap each other.

Abstract: Techniques are described for providing geographically-related search results in map interfaces that are derived with an understanding of the intent behind the user's query, and the abstract entities to which the query maps.

Abstract: A search engine computer system is configured to produce an optimized display of maps especially useful in mobile handheld devices with comparatively small screens. The system factors in scoring functions, visibility, and empirical data on map levels to provide optimal map based results to users. This minimizes or avoids graphical results that overlap each other.

Abstract: A tracking method for a tracking system that includes target and tracking devices includes the steps of: in response to a location request issued by the tracking device and transmitted through a wireless telecommunications network, enabling operation of the target device to access a location-based service that is provided by the wireless telecommunications network and to generate a location information signal from the location-based service that is subsequently transmitted to the target device through the wireless telecommunications network such that an immediate vicinity of the target device can be located; and, in response to a tracking request from the tracking device, enabling the target device to transmit a beaconing signal wirelessly such that an exact location of the target device can be determined based on the beaconing signal.

Abstract: Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein, including special vapor prime and development operations.

Abstract: For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.

Abstract: Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein. The method may comprise employing an anti reflective coating prior to applying a photo resist coating in a semiconductor manufacturing process. Also disclosed are methodologies for exhausting resist residue during development via a rinsing fluid.

Abstract: A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A second low k dielectric layer is formed on the first low k dielectric layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Further etching of the first dielectric layer is prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

Abstract: A method of forming a dual damascene structure in a semiconductor device arrangement forms a first dielectric layer made of an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first dielectric layer, and a second dielectric layer, made of low k dielectric material, is formed on the nitride etch stop layer. A via is etched into the first dielectric layer, and a trench is then etched into the second dielectric layer. The materials if the first and second dielectric layers are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second dielectric layer and not the first dielectric layer.

Abstract: A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the nitride etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

Abstract: A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A second low k dielectric layer is formed on the first low k dielectric layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Further etching of the first dielectric layer is prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

Abstract: A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

Abstract: A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A trench is etched into the second low k dielectric layer, followed by the etching of a via into the first low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the first low k dielectric material and not the second low k dielectric material.

Abstract: A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the oxide dielectric layer, and a low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the low k dielectric layer, followed by the etching of a via into the oxide dielectric layer. The oxide dielectric material and low k dielectric material are selected so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the oxide dielectric material and not the low k dielectric material.

Abstract: A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the second low k dielectric layer, followed by the etching of a via into the first low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the first low k dielectric material and not the second low k dielectric material.