Abstract: A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802.3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The transmit state machine outputs a flush transmit buffer signal to the transmit memory management unit in response to a detected error in transmitting the transmit data.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. Read and write counters are each implemented as gray code counters that increment a corresponding pointer value by changing a single bit. A synchronization circuit selectively sets a full or empty flag based on an asynchronous comparison of the read and write pointer values. Use of gray code counters for the read pointer value and write pointer value ensures accurate comparisons in a multi-clock environment.

Abstract: A novel method of power management is provided in a computer system having a network interface module including a buffer memory and a MAC block. The method includes determining whether the system is inactive during a predetermined time period. If so, activity of the MAC block is checked. If the MAC block is idle, the status of the buffer memory is determined. The system is placed into a power-down mode if the buffer memory is empty.

Abstract: A network interface for a workstation is configured to supply data to a host bus. The network interface includes a buffer memory for storing a data frame received from a network according to a first byte alignment. A bus interface unit is configured to output the data frame onto the host bus according to a second byte alignment based on a master or slave transfer request to access the buffer memory. The slave request to access the buffer memory may be in the form of either an I/O mapped or memory mapped request. A memory management unit includes request logic to receive the master and slave transfer requests and generate a generic request to access the buffer memory. The memory management unit is configured to transfer the data frame from the buffer memory in response to the generic request. The bus interface unit includes a byte packing circuit configured for changing a byte alignment of the data frame prior to its transfer to the host memory.

Abstract: A network interface has a static random access memory (SRAM) that outputs ordered data to a target by using a first and second holding register, and an output holding register. The SRAM supplies a data set to the first holding register which supplies the first data set to the second holding register. The SRAM also replenishes the first holding register with a second data set. A multiplexer selectively supplies the data set stored in one of the two holding registers to the output holding register which supplies that data set to a bus connected to the target. A bus interface unit state machine supplies a select signal to the multiplexer to control the selection between the first and second holding registers. The state machine generates the select signal based on a bus access controller detecting a target ready signal generated by the target indicating the target's readiness to receive a data set. The select signal enables the multiplexer to supply the next ordered data set to the output holding register.

Abstract: A network interface includes a multiplexer that selectively supplies either a stored address from an address holding register, or a reload address from a reload address holding register, to a random access buffer memory based on a done delay signal (DMA_DONE_DLY). The done delay signal is generated by an advance signal generator in response to detection of a target initiated termination request on the PCI bus during a DMA data transfer from the random access buffer memory to the target. if the PCI bus transfer is interrupted, the reload address is supplied to the random access buffer memory to enable data output holding registers to be reloaded with the data lost by the target during the interrupted DMA transfer. The array of data output holding registers are capable of recovering from the interrupted PCI bus transfer and output the data set which the target (e.g., the host system memory) expects to receive.

Abstract: A network interface device includes a random access transmit buffer and a random access receive buffer for transmission and reception of transmission and receive data frames between a host computer bus and a packet switched network. The network interface device includes a memory management unit having read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memories between the read and write controllers. The synchronization circuit asynchronously monitors the amount of data stored in the random access transmit and receive buffer by asynchronously comparing write pointer and read pointer values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The read and write controllers output status information corresponding to the reading or writing of a stored data frame in the receive buffer. The memory management unit includes a synchronization circuit, which arbitrates updates to the holding registers by the read and write controllers based on the asynchronously determined presence of at least one stored data frame.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal.

Abstract: A network interface device minimizes access latency in initiating a DMA transfer request by selectively supplying a long bit comparison result, generated in a write controller configured for writing data into a buffer memory, directly to a read controller based on a determination that the buffer memory stores less than one complete frame. The media access controller determines the length of the data frame, and supplies the determined length to the write controller. The write controller compares the determined length to a prescribed threshold, and outputs a long bit value for storage in a buffer memory location contiguous with the stored data frame. The long bit can then be used to select a receive buffer threshold optimized for larger frames.

Abstract: A network interface device having a random access memory for buffering data between a host bus interface and a media access controller includes a buffer controller configured for storing a data frame in combination with tracking and status information associated with the storage of the data frame. The memory controller is configured for writing receive frame data received from a media access controller into the random access memory. The tracking and status information is stored in memory locations contiguous with the data frame to enable a read controller operating in a separate clock domain to access the status information and the corresponding data frame as a single data unit. Moreover, the disclosed embodiment stores the status information at the beginning of the stored data unit, enabling a controller reading the buffer memory to immediately determine the status of the corresponding stored data frame.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal.

Abstract: A network interface device having a random access memory for buffering data between a host bus interface and a media access controller includes a buffer controller configured for storing a data frame in combination with tracking and status information associated with the storage of the data frame. The memory controller is configured for writing transmit frame data received from a host bus into the random access memory, and generating tracking information based on transfer status signals corresponding to the transfer of the data frame from either a master transfer mode or a slave transfer mode. Hence, the amount of logic associated with generating the tracking, control and/or status information is independent of the nature of the transfer from the host bus. The tracking and status information is stored in memory locations contiguous with the data frame to enable a read controller to access the status information and the corresponding data frame as a single data unit.