Abstract: A circuit includes a level shifter circuit, an output circuit, and a first feedback circuit. The level shifter circuit is coupled to a first voltage supply, and configured to receive an enable signal, a first input signal or a second input signal, and to generate a first and second signal responsive to the enable signal or the first input signal. The output circuit coupled to the level shifter circuit and the first voltage supply, and configured to generate an output signal or a first feedback signal responsive to the first signal, and configured to latch a previous state of the output signal in response to the enable signal or an inverted enable signal. The first feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and configured to receive at least the enable signal, the inverted enable signal or the first feedback signal.

Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master latch including a transmission circuit, and a slave latch including a first feedback inverter. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the transmission circuit includes a third transistor configured to receive the third clock signal.

Abstract: A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

Abstract: An integrated circuit includes a first power rail extending in a first direction, and configured to supply a first supply voltage, and a first region next to the first power rail. The first region includes a first conductive structure extending in the first direction, a first set of conductive structures extending in a second direction, and a first set of vias between the first set of conductive structures and the first conductive structure. The first set of conductive structures overlaps the first conductive structure and the first power rail, and is located on a second level. Each conductive structure of the first set of conductive structures is separated from each other in the first direction. Each via of the first set of vias is located where the first set of conductive structures overlaps the first conductive structure and couples the first set of conductive structures to the first conductive structure.

Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.

Abstract: A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

Abstract: A method for a hard reset of a target electronic device includes establishing a near field communications (NFC) channel to the target electronic device, receiving a wireless signal at the target electronic device over the NFC channel, and comparing a signature of the received wireless signal with a predefined characteristic signature of a reset command signal. Responsive to the comparing, the method includes generating a reset signal resetting the target electronic device.

Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.

Abstract: A method for a hard reset of a target electronic device includes establishing a near field communications (NFC) channel to the target electronic device, receiving a wireless signal at the target electronic device over the NFC channel, and comparing a signature of the received wireless signal with a predefined characteristic signature of a reset command signal. Responsive to the comparing, the method includes generating a reset signal resetting the target electronic device.

Abstract: An exterior bowl has a closed bottom, an open top, and a side wall there between. An exterior annular flange extends radially outwardly from the open top of the exterior bowl. An interior bowl has an open bottom, an open top, and a side wall there between. An interior annular flange extends radially outwardly from the open top of the interior bowl. The open bottom of the interior bowl is coupled to the closed bottom of the exterior bowl to create an annular chamber between the side wall of the exterior bowl and the side wall of the interior bowl. Tubing within the chamber in a spiral configuration removably receives a plurality of surgical wires. Each of the surgical wires has an upper extent extending upwardly and out of the chamber for being grasped and extracted from the tubing.

Abstract: Disclosed are methods for imaging lumen-forming structures such as blood vessels using near-infrared fluorescence in the NIR-II region of 1000-1700 nm. The fluorescence is created by excitation of solubilized nano-structures that are delivered to the structures, such as carbon nanotubes, quantum dots or organic molecular fluorophores attached to hydrophilic polymers. These nanostructures fluoresce in the NIR-II region when illuminated through the skin and tissues. Fine anatomical vessel resolution down to ?30 ?m and high temporal resolution up to 5-10 frames per second is obtained for small-vessel imaging with up to 1 cm penetration depth in mouse hind limb, which compares favorably to tomographic imaging modalities such as CT and MRI with much higher spatial and temporal resolution, and compares favorably to scanning microscopic imaging techniques with much deeper penetration.

Abstract: Disclosed are methods for imaging lumen-forming structures such as blood vessels using near-infrared fluorescence in the NIR-II region of 1000-1700 nm. The fluorescence is created by excitation of solubilized nano-structures that are delivered to the structures, such as carbon nanotubes, quantum dots or organic molecular fluorophores attached to hydrophilic polymers. These nanostructures fluoresce in the NIR-II region when illuminated through the skin and tissues. Fine anatomical vessel resolution down to ?30 ?m and high temporal resolution up to 5-10 frames per second is obtained for small-vessel imaging with up to 1 cm penetration depth in mouse hind limb, which compares favorably to tomographic imaging modalities such as CT and MRI with much higher spatial and temporal resolution, and compares favorably to scanning microscopic imaging techniques with much deeper penetration.

Abstract: The present invention is directed to a display device which comprises two layers of insulating substrate, at least the substrate on the viewing side is transparent, an array of display cells sandwiched between the two layers of substrate, a writing means, and optionally an erasing means to magnetically or electrically erase the image. The display cells are filled with a dispersion of magnetic particles which may be charged or non-charged. The display of the invention eliminates the use of the transparent conductor film, such as ITO, on the viewing side. Therefore, the displays of this invention are more cost effective, more flexible and durable and capable of higher image contrast ratio and higher reflectance in the Dmin area.

Abstract: Structures and manufacturing processes of an ACF array using a non-random array of microcavities of predetermined configuration, shape and dimension. The manufacturing process includes fluidic filling of conductive particles onto a substrate or carrier web comprising a predetermined array of microcavities, of selective metallization of the array followed by filling the array with a filler material and a second selective metallization on the filled microcavity array. The thus prepared filled conductive microcavity array is then over-coated or laminated with an adhesive film. Cavities in the array, and particles filling the cavities, can have a unimodal, bimodal, or multimodal distribution.

Abstract: Structures and manufacturing processes of an ACF array using a non-random array of microcavities of predetermined configuration, shape and dimension. The manufacturing process includes fluidic filling of conductive particles onto a substrate or carrier web comprising a predetermined array of microcavities, or selective metallization of the array followed by filling the array with a filler material and a second selective metallization on the filled microcavity array. The thus prepared filled conductive microcavity array is then over-coated or laminated with an adhesive film. Cavities in the array, and particles filling the cavities, can have a unimodal, bimodal, or multimodal distribution.

Abstract: A system and method are disclosed for reducing reverse bias in an electrophoretic display. The system and method include the application of varying levels of voltages across an array of electrophoretic display cells of the electrophoretic display to move the cells towards a stable state in a driving cycle. In addition, the system and method disconnect the voltages from the electrophoretic display cells at a time duration prior to reaching step transitions of the voltages during the driving cycle. Pre-driving approaches apply a first pre-driving voltage at a first polarity to the display cells before driving the display cells with a second driving voltage at a second, opposite polarity. Varying the time duration and amplitude of the pre-driving signals produces further beneficial reduction in reverse bias.

Abstract: An electrophoretic display (EPD) with thermal control is disclosed for controlling and maintaining an image in extreme temperature environments. Techniques are also disclosed for maintaining the EPD cell threshold voltage for EPD cells comprising an EPD display media at or above a desired level in an environment in which the EPD may be subjected to an extreme temperature. The techniques comprise sensing a sensed temperature associated with the EPD display media, determining whether the sensed temperature satisfies a criterion established to ensure that the display media temperature remains at a level associated with an acceptable EPD cell threshold voltage, and in the event it is determined that the sensed temperature does not satisfy the criterion, controlling the EPD display media temperature as required to bring the sensed temperature to a level that satisfies the criterion.

Abstract: A hand-held, portable, contact scanner using CCD scanning technology in conjunction with power regulation, noise reduction and image stitching. The scanner uses various movement tracking technologies to determine when the scanner is in contact with a document to be scanned. A dual roller system is used to effectively track motion of a contact scanner 100 across a target document. Alternatively, movement detection is performed by a reflected laser or infra-red (IR) output.