Abstract: Methods and apparatus for efficient scaling of fabric architectures such as those based on PCIe technology, including up to very large fabrics and numbers of hosts/devices for use in ultra-high performance applications such as for example data centers and computing clusters. In one aspect, methods and apparatus for using Non-Transparent Bridge (NTB) technology to export Message Signaled Interrupts (MSIs) to external hosts are described. In a further aspect, an IO Virtual Address (IOVA) space is created is used as a method of sharing an address space between hosts, including across the foregoing NTB(s). Additionally, a Fabric Manager (FM) entity is disclosed and utilized for programming e.g., PCIe switch hardware to effect a desired host/fabric configuration.

Abstract: Methods and apparatus for efficient scaling of fabric architectures such as those based on PCIe technology, including up to very large fabrics and numbers of hosts/devices for use in ultra-high performance applications such as for example data centers and computing clusters. In one aspect, methods and apparatus for using Non-Transparent Bridge (NTB) technology to export Message Signaled Interrupts (MSIs) to external hosts are described. In a further aspect, an IO Virtual Address (IOVA) space is created is used as a method of sharing an address space between hosts, including across the foregoing NTB(s). Additionally, a Fabric Manager (FM) entity is disclosed and utilized for programming e.g., PCIe switch hardware to effect a desired host/fabric configuration.

Abstract: Systems and methods are provided for performing write-with-response operations in a network on a chip architecture. In response to receiving an instruction to perform a write-with-response operation, a writer computing resource of a computing system (implemented using the network on a chip architecture) executes this instruction by performing a write operation for writing data to a memory location followed by a response operation for notifying a notification target computing resource of the computing system that the data has been written to the memory location.

Abstract: Systems and methods to be used by a processing element from among multiple computing resources of a computing system, where communication between the computing resources is carried out based on network on a chip architecture, to send first data from memory registers of the processing element and second data from memory of the computing system to a destination processing element from among the multiple computing resources, by sending the first data to a memory controller of the memory along with a single appended-read command.

Abstract: Systems and methods are provided for performing write-with-response operations in a network on a chip architecture. In response to receiving an instruction to perform a write-with-response operation, a writer computing resource of a computing system (implemented using the network on a chip architecture) executes this instruction by performing a write operation for writing data to a memory location followed by a response operation for notifying a notification target computing resource of the computing system that the data has been written to the memory location.

Abstract: Systems and methods to be used by a processing element from among multiple computing resources of a computing system, where communication between the computing resources is carried out based on network on a chip architecture, to send first data from memory registers of the processing element and second data from memory of the computing system to a destination processing element from among the multiple computing resources, by sending the first data to a memory controller of the memory along with a single appended-read command.