Patents by Inventor Jerry D. Ackaret
Jerry D. Ackaret has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10327361Abstract: Managing thermal cycles of air temperature within a server rack includes: monitoring air temperature within the server rack; determining that the monitored temperature has fallen below a predetermined minimum threshold; and increasing air temperature within the server rack including capturing warm ambient air.Type: GrantFiled: April 7, 2017Date of Patent: June 18, 2019Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Jerry D. Ackaret, Fred A. Bower, III, Gary D. Cudak, Caihong Zhang
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Patent number: 10180866Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.Type: GrantFiled: February 23, 2015Date of Patent: January 15, 2019Assignee: International Business Machines CorporationInventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffrey J. Van Heuklon
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Publication number: 20180295753Abstract: Managing thermal cycles of air temperature within a server rack includes: monitoring air temperature within the server rack; determining that the monitored temperature has fallen below a predetermined minimum threshold; and increasing air temperature within the server rack including capturing warm ambient air.Type: ApplicationFiled: April 7, 2017Publication date: October 11, 2018Inventors: JERRY D. ACKARET, FRED A. BOWER, III, GARY D. CUDAK, CAIHONG ZHANG
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Patent number: 9389937Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.Type: GrantFiled: November 19, 2013Date of Patent: July 12, 2016Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Jerry D. Ackaret, Sumeet Kochar, Randolph S. Kolvick, Wilson E. Smith
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Patent number: 9081676Abstract: Operating computer memory in a computer including dynamically monitoring, by a predictive failure analysis (‘PFA’) module, correctable memory errors and memory temperature and managing cooling resources in the computer in dependence upon the correctable memory errors and memory temperature.Type: GrantFiled: June 2, 2009Date of Patent: July 14, 2015Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Jerry D. Ackaret, Robert M. Dunn, Anna H. Siskind, Wilson E. Smith
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Publication number: 20150186230Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.Type: ApplicationFiled: February 23, 2015Publication date: July 2, 2015Inventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffrey J. Van Heuklon
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Publication number: 20150143054Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Inventors: Jerry D. Ackaret, Sumeet Kochar, Randolph S. Kolvick, Wilson E. Smith
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Publication number: 20150143052Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.Type: ApplicationFiled: November 19, 2013Publication date: May 21, 2015Applicant: International Business Machines CorporationInventors: JERRY D. ACKARET, SUMEET KOCHAR, RANDOLPH S. KOLVICK, WILSON E. SMITH
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Patent number: 9003223Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.Type: GrantFiled: September 27, 2012Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffery J. Van Heuklon
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Publication number: 20140089725Abstract: Effects of a physical memory fault are mitigated. In one example, to facilitate mitigation, memory is allocated to processing entities of a computing environment, such as applications, operating systems, or virtual machines, in a manner that minimizes impact to the computing environment in the event of a memory failure. Allocation includes using memory structure information, including, information regarding fault containment zones, to allocate memory to the processing entities. By allocating memory based on fault containment zones, a fault only affects a minimum number of processing entities.Type: ApplicationFiled: September 27, 2012Publication date: March 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jerry D. Ackaret, Robert M. Dunn, Susan E. Goodwin, Sumeet Kochar, Randolph S. Kolvick, James A. O'Connor, Wilson E. Smith, Jeffery J. Van Heuklon
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Patent number: 8635488Abstract: A method and circuit for implementing an enhanced availability personality card for a chassis computer system, and a design structure on which the subject circuit resides are provided. The personality card includes a first erasable programmable read only memory (EPROM) and a second EPROM, each EPROM storing Vital Product Data (VPD) and a first temperature sensor and a second temperature sensor sensing temperature. A primary bidirectional bus and a redundant bidirectional bus are respectively connected between the first EPROM and the first temperature sensor and the second EPROM and the second temperature sensor, and a pair of chassis management modules. Each chassis management module includes a switch connected to both the primary bidirectional bus and the redundant bidirectional bus providing redundant paths, enabling continued function with failure of any critical personality card component.Type: GrantFiled: November 8, 2011Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Jerry D. Ackaret, Justin P. Bandholz, Brian E. Bigelow, Joseph E. Bolan, Kevin M. Cash, David L. Cowell, Martin J. Crippen, Christopher L. Durham, Jeffery M. Franke, James E. Hughes, David J. Jensen, John K. Langgood, Bay Van Nguyen, James A. O'Connor, Derek Robertson, John M. Sheplock, Wilson E. Smith
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Publication number: 20130117601Abstract: A method and circuit for implementing an enhanced availability personality card for a chassis computer system, and a design structure on which the subject circuit resides are provided. The personality card includes a first erasable programmable read only memory (EPROM) and a second EPROM, each EPROM storing Vital Product Data (VPD) and a first temperature sensor and a second temperature sensor sensing temperature. A primary bidirectional bus and a redundant bidirectional bus are respectively connected between the first EPROM and the first temperature sensor and the second EPROM and the second temperature sensor, and a pair of chassis management modules. Each chassis management module includes a switch connected to both the primary bidirectional bus and the redundant bidirectional bus providing redundant paths, enabling continued function with failure of any critical personality card component.Type: ApplicationFiled: November 8, 2011Publication date: May 9, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jerry D. Ackaret, Justin P. Bandholz, Brian E. Bigelow, Joseph E. Bolan, Kevin M. Cash, David L. Cowell, Martin J. Crippen, Christopher L. Durham, Jeffery M. Franke, James E. Hughes, David J. Jensen, John K. Langgood, Bay Van Nguyen, James A. O'Connor, Derek Robertson, John M. Sheplock, Wilson E. Smith
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Publication number: 20100306598Abstract: Operating computer memory in a computer including dynamically monitoring, by a predictive failure analysis (‘PFA’) module, correctable memory errors and memory temperature and managing cooling resources in the computer in dependence upon the correctable memory errors and memory temperature.Type: ApplicationFiled: June 2, 2009Publication date: December 2, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jerry D. Ackaret, Robert M. Dunn, Anna H. Siskind, Wilson E. Smith
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Patent number: 7238547Abstract: An IC device is packaged for accelerated transient particle emission by doping the underfill thereof with a transient-particle-emitting material having a predetermined, substantially constant emission rate. The emission rate may be tunable. In one aspect, a radioactive adhesive composition is provided for bonding a semiconductor device to a chip carrier. The radioactive adhesive composition is made from a cured reaction product including a resin and a filler, and may be reworkable or non-reworkable. Either the resin or the filler, individually or both together as a mix, are doped substantially uniformly with the transient-particle-emitting material, thereby putting the transient-particle-emitting in close proximity with the IC to be tested. The underfill is formulated to have a stable chemistry, and the doped particles are encapsulated, so as to contain the emissions. Accelerated transient-particle-emission testing may then be performed on the IC in situ to provide accelerated detection of soft errors.Type: GrantFiled: April 4, 2005Date of Patent: July 3, 2007Assignee: International Business Machines CorporationInventors: Janes Jones, legal representative, Jerry D. Ackaret, Michael A. Gaynes, Michael S. Gordon, Nancy C. LaBianca, Theodore H. Zabel, deceased
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Patent number: 7084660Abstract: A method and system are provided for accelerated detection of soft error rates (SER) in integrated circuits (IC's) due to transient particle emission. An integrated circuit is packaged for accelerated transient particle emission by doping the underfill thereof with a transient-particle-emitting material having a predetermined emission rate. The emission rate is substantially constant over a predetermined period of time for testing. Accelerated transient-particle-emission testing is performed on the integrated circuit. Single-event upsets due to soft errors are detected, and a quantitative measurement of SER is determined.Type: GrantFiled: April 4, 2005Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Jerry D. Ackaret, Richard B. Bhend, David F. Heidel, Naoko Pia Sanda, Scott B. Swaney, Jane Jones, legal representative, Theodore H. Zabel, deceased