Abstract: Apparatus for assigning addresses to devices connected to a small computer system interface (SCSI) bus. A second configure bus interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

Abstract: An apparatus and method for protecting BIOS stored on a direct access storage device into a personnal computer system. The personal computer system comprises a system processor, a system planar, a random access main memory, a read only memory, a protection means and at least one direct access storage device. The read only memory includes a first portion of BIOS and data representing the type of system processor and system planar I/O configuration. The first portion of BIOS initializes the system and the direct access storage device, and resets the protection means in order to read in a master boot record into the random access memory from a protectable partition on the direct access storage device.

Abstract: In a DASD caching system, in which pages of sectors of data are stored by reading in a desired sector and prefetching a plurality of adjacent sectors for later access, errors in disk storage media cause error signals to be generated. Such errors are handled by storing indications of which sectors have errors and which do not, and accessing such indications in response to later requests for such sectors. Such indications are stored in each page in the cache. Further, a history is maintained of which pages and sectors therein, were placed in the cache in the past.

Abstract: A redundant error-detecting addressing code for use in a cache memory. A directory converts logical data addresses to physical addresses in the cache where the data is stored in blocks. The blocks are expanded to include redundant addressing information such as the logical data address and the physical cache address. When a block is accessed from the cache, the redundant addressing is compared to the directory addressing information to confirm that the correct data has been accessed.

Abstract: In a data processing system of the type wherein a host processor transfers data to or from a plurality of attachment devices, a cache memory is provided for storing blocks of data which are most likely to be needed by the host processor in the near future. The host processor can then merely retrieve the necessary information from the cache memory without the necessity of accessing the attachment devices. When transferring data to cache from an attachment disk, additional unrequested information can be transferred at the same time if it is likely that this additional data will soon be requested. Further, a directory table is maintained wherein all data in cache is listed at a "home" position and, if more than one block of data in cache have the same home position, a conflict chain is set-up so that checking the contents of the cache can be done simply and quickly.

Abstract: When transferring data to a cache memory from an attachment data storage device, additional unrequested information can be transferred at the same time if it is likely that this additional data will soon be requested. The average quantity of data transferred to the cache memory in each operation can be automatically and continually varied in order to maximize the performance advantage provided by the cache memory. When a record of data is requested by the host processor, data is transferred to the cache memory from an attachment data storage device in increments of fixed-length data blocks each containing a sequence of data records, with the number of transferred blocks being determined by the position of a requested data record in its respective data block, and the average number of blocks transferred in any one operation being varied by adjusting threshold position values at which second or third data blocks are transferred.

Abstract: A method and apparatus for performing data base searches in which the host processor and main memory are free for other processing tasks between the time that the host processor requests the search until the search results are reported back to the host processor. To commence the search, an input/output controller communicates from the host processor to a record scan circuit values of a skip length, a key length and a data length. While data records are received serially from disk files, within each data record, a length of data equal to the specified skip length is initially skipped. Following this, a search argument is compared with a length of data specified by the key length value. This comparison operation is alternated with skipping of data specified by the data length value until the end of the record is reached or until a specified number of comparisons has taken place. The data record is stored as it is received from the files.

Abstract: Serial storage interface apparatus for coupling a serial storage mechanism, such as a charge coupled storage device or a magnetic bubble storage device, to a data processor input/output (I/O) bus. Speed control circuitry is provided for causing the serial storage mechanism to operate at a higher speed when the data processor is responding more rapidly to data transfer requests from the interface apparatus and at a lower speed when the data processor is responding less rapidly to data transfer requests from the interface apparatus. This speed adjustment feature reduces the amount of data buffering required for interfacing a serial storage mechanism to an asynchronous variable response time I/O bus system.

Abstract: A data processor input/output controller which is particularly useful as a microcontroller for the transfer of data between a host processor and one or more peripheral input/output devices in a digital data processing system. This input/output (I/O) controller is a subchannel controller for offloading a goodly portion of the subchannel control function from the host processor. This I/O controller includes a microprocessor for assisting and supervising the controller internal operations. Also included in the controller is an automatic high-speed data bypass mechanism whereby data may be transferred from the host processor to the I/O device or vice versa without having to pass through the microprocessor and without requiring any intervention on the part of the microprocessor during such automatic transfer.

Abstract: In a data processing system, a mechanism provides independent assignment of page locations for a program's instructions and its data and better enables control to be transferred between programs, or portions thereof, that reside at different addresses in different pages of a multiple page instruction store. The initial linkage is established through the use of a Branch And Link instruction. Subsequent linkages are established through the use of Return and Link instructions, each of which transfers control to a previous program, or program segment, while simultaneously establishing the linkage for a subsequent return to this program or program segment.INTRODUCTIONCROSS REFERENCES TO RELATED APPLICATIONSU.S. Patent application of J. D. Dixon, one of the co-inventors herein, Ser. Nos. 866,425, filed Jan. 3, 1978 and 918,223, filed of even date herewith, both assigned to the assignee of the present invention, show and describe, but do not claim, portions of the invention claimed in the present invention.

Abstract: In a data processing system, a mechanism for enabling control to be transferred between programs, or portions thereof, that reside at different addresses in an instruction store. The initial linkage is established through the use of a Branch And Link instruction. Subsequent linkages are established through the use of Return And Link instructions, each of which causes the mechanism to transfer control to a previous program, or program segment, while simultaneously establishing the linkage for a subsequent return to this program or program segment.