Abstract: A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which allows test results to be determined on the device. Test results are stored temporarily in one or more latch elements on the semiconductor device and are subsequently stored in nonvolatile memory elements. The invention eliminates the need for device testing equipment to perform a determination of test results and thus may simplify the design of test equipment. In one embodiment of the invention, passing test results are stored in a mixed code of set and unset nonvolatile memory elements such that the test results contain information about correct application of test signals as well as correct functioning of the semiconductor device.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: A method and system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which allows test results to be determined on the device. Test results are stored temporarily in one or more latch elements on the semiconductor device and are subsequently stored in nonvolatile memory elements. The invention eliminates the need for device testing equipment to perform a determination of test results and thus may simplify the design of test equipment. In one embodiment of the invention, passing test results are stored in a mixed code of set and unset nonvolatile memory elements such that the test results contain information about correct application of test signals as well as correct functioning of the semiconductor device.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Abstract: A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which allows test results to be determined on the device. Test results are stored temporarily in one or more latch elements on the semiconductor device and are subsequently stored in nonvolatile memory elements. The invention eliminates the need for device testing equipment to perform a determination of test results and thus may simplify the design of test equipment. In one embodiment of the invention, passing test results are stored in a mixed code of set and unset nonvolatile memory elements such that the test results contain information about correct application of test signals as well as correct functioning of the semiconductor device.

Abstract: An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.