Abstract: A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided with routing logic to enable to ECBs to be utilized for either book-to-book routing or routing within the same processor book. A table specific wiring scheme is provided for coupling the ECBs running off the chips of one MCM to the chips of the second MCM on the processor book so that the chips of the first MCM are connected directly to the chips of a second MCM that is logically furthest away and vice versa. Once the wiring of the ECBs are completed according to the wiring scheme, the operational and functional characteristics reflect those of a processor book configured for technical workloads.

Abstract: The illustrative embodiments provide a computer implemented method and apparatus for modifying an existing circuit design. For a modification in a design of a circuit, the circuit design tool receives a code describing the modification, and a design of the circuit. The design of the circuit includes a first design, which includes a design for a number of metallic layers in the circuit. The design of the circuit further includes a second design, which includes and a design for a number of non-metallic layers in the circuit. The circuit design tool identifies a set of hooks, a set of disconnected components, and a set of filler cells in the design of the circuit. The circuit design tool produces a modification design, which is implemented in a revision of the first design, using the code, and one or more of the hooks, the disconnected components, and the filler cells.

Abstract: A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided with routing logic to enable to ECBs to be utilized for either book-to-book routing or routing within the same processor book. A table specific wiring scheme is provided for coupling the ECBs running off the chips of one MCM to the chips of the second MCM on the processor book so that the chips of the first MCM are connected directly to the chips of a second MCM that is logically furthest away and vice versa. Once the wiring of the ECBs are completed according to the wiring scheme, the operational and functional characteristics reflect those of a processor book configured for technical workloads.

Abstract: The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second processing units. Each of the first and second processing units has a respective first output data bus. The first output data bus of the first processing unit is coupled to the second processing unit, and the first output data bus of the second processing unit is coupled to the first processing unit. At least the first processing unit of the first processing book and the second processing unit of the second processing book each have a respective second output data bus.

Abstract: An apparatus for performing bus tracing with scalable bandwidth in a distributed memory symmetric multiprocesssor system is disclosed. The distributed memory symmetric multiprocessor system includes multiple processing units, each coupled to a memory module. Each of the processing units includes a memory controller and a bus trace macro (BTM) module. The memory controller is coupled to an interconnect for the symmetric multiprocessor system, and the BTM module is connected between the interconnect and the memory controller via two multiplexors. A subset of the BTM modules within the symmetric multiprocessor system is enabled for performing tracing operations such that address transactions on the interconnect are divided among the subset of the BTM modules to be selectively and separately intercepted by each BTM module within the subset of the BTM modules.

Abstract: An apparatus for performing imprecise bus tracing in a distributed memory symmetric multiprocessor system is disclosed. The apparatus includes a bus trace macro (BTM) module that can control the snoop traffic seen by one or more of the memory controllers in the data processing system and utilize a local memory attached to the memory controller for storing trace records. After the BTM module is enabled for tracing operations, the BTM module snoops transactions on the interconnect and packs information contained within these transactions into a block of data of a size that matches the write buffers within the memory controller. In addition, the BTM module also includes a dropped record counter for counting the number of address transactions that were not converted to trace records because all the write buffers were completely full. After an occurence of the write buffers full condition, a time stamp trace record is inserted before a new trace record can be written.

Abstract: A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a data processing system includes at least first through third processing units, data storage coupled to the plurality of processing units, and an interconnect fabric. The interconnect fabric includes at least a first data bus coupling the first processing unit to the second processing unit and a second data bus coupling the third processing unit to the second processing unit so that the first and third processing units can transmit data traffic to the second processing unit. The data processing system further includes a control channel coupling the first and third processing units.

Abstract: The symmetric multiprocessor system includes multiple processing nodes, with multiple agents at each node, connected to each other via an interconnect. A request transaction is initiated by a master agent in a master node to all receiving nodes. A write counter number is generated for associating with the request transaction. The master agent then waits for a combined response from the receiving nodes. After the receipt of the combined response, a data packet is sent from the master agent to all intended one of the receiving nodes according to the combined response. After the data packet has been sent, the master agent in the master node is ready to send another request transaction along with a new write counter number, without the necessity of waiting for an acknowledgement from the receiving node.

Abstract: A computer system of a number of processing nodes operate either in a loop configuration or off of a common bus with high speed, high performance wide bandwidth characteristics. The processing nodes in the system are also interconnected by a separate narrow bandwidth, low frequency recovery bus. When problems arise with node operations on the high speed bus, operations are transferred to the low frequency recovery bus and continue there at a slower rate for recovery operations. The recovery technique may be used to increase system speed and performance on a dynamic basis.

Abstract: A data processing system includes a plurality of nodes, which each contain at least one agent and each have an associated node identifier, and memory distributed among the plurality of nodes. The data processing system further includes an interconnect containing a segmented data channel, where each node contains a segment of the segmented data channel and each segment is coupled to at least one other segment by destination logic. In response to snooping a write request of a master agent on the interconnect, a target agent that will service the write request places its node identifier in a snoop response. When the master agent receives the combined response, which contains the node identifier of the target agent, the master agent issues on the segmented data channel a write data transaction specifying the node identifier of the target agent as a destination identifier.

Abstract: A method and system for providing a multiprocessor processor book that is utilized as a building block for a large scale data processing system. Two 4-way multi-chip modules (MCM) are utilized to create the processor book. The first and second MCMs are configured with normal wiring among their respective processors. An additional wiring is provided that links external buses of each chip of the first MCM with buses of a corresponding chip of the second MCM and vice versa. The additional wiring enables each processor of the first MCM substantially direct access to the distributed memory components of the next MCM with no affinity. The processor book is plugged into a processor rack configured to receive multiple processor books that together make up the large scale data processing system.

Abstract: A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams. If an error is detected in a particular hardware partition, the data stream assigned to that hardware partition is reassigned to another of the plurality of hardware partitions, thus preventing an error in one of the hardware partitions from resulting in a catastrophic failure.

Abstract: A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided with routing logic to enable to ECBs to be utilized for either book-to-book routing or routing within the same processor book. A table specific wiring scheme is provided for coupling the ECBs running off the chips of one MCM to the chips of the second MCM on the processor book so that the chips of the first MCM are connected directly to the chips of a second MCM that is logically furthest away and vice versa. Once the wiring of the ECBs are completed according to the wiring scheme, the operational and functional characteristics reflect those of a processor book configured for technical workloads.

Abstract: An apparatus for performing in-memory bus tracing in a data processing system having a distributed memory is disclosed. The apparatus includes a bus trace macro (BTM) module that can control the snoop traffic seen by one or more of the memory controllers in the data processing system and utilize a local memory attached to the memory controller for storing trace records. After the BTM module is enabled for tracing operations, the BTM module snoops transactions on the interconnect and packs information contained within these transactions into a block of data of a size that matches the write buffers within the memory controller.

Abstract: An apparatus for performing bus tracing with scalable bandwidth in a distributed memory symmetric multiprocesssor system is disclosed. The distributed memory symmetric multiprocessor system includes multiple processing units, each coupled to a memory module. Each of the processing units includes a memory controller and a bus trace macro (BTM) module. The memory controller is coupled to an interconnect for the symmetric multiprocessor system, and the BTM module is connected between the interconnect and the memory controller via two multiplexors. A subset of the BTM modules within the symmetric multiprocessor system is enabled for performing tracing is operations such that address transactions on the interconnect are divided among the subset of the BTM modules to be selectively and separately intercepted by each BTM module within the subset of the BTM modules.

Abstract: An apparatus for performing imprecise bus tracing in a distributed memory symmetric multiprocessor system is disclosed. The apparatus includes a bus trace macro (BTM) module that can control the snoop traffic seen by one or more of the memory controllers in the data processing system and utilize a local memory attached to the memory controller for storing trace records. After the BTM module is enabled for tracing operations, the BTM module snoops transactions on the interconnect and packs information contained within these transactions into a block of data of a size that matches the write buffers within the memory controller. In addition, the BTM module also includes a dropped record counter for counting the number of address transactions that were not converted to trace records because all the write buffers were completely full. After an occurence of the write buffers full condition, a time stamp trace record is inserted before a new trace record can be written.

Abstract: A method, system, and processor cache configuration that enables efficient retrieval of valid data in response to an invalidate cache miss at a local processor cache. A cache directory is provided a set of directional bits in addition to the coherency state bits and the address tag. The directional bits provide information that includes a processor cache identification (ID) and routing method. The processor cache ID indicates which processor's operation resulted in the cache line of the local processor changing to the invalidate (I) coherency state. The routing method indicates what transmission method to utilize to forward the cache line, from among a local system bus or a switch or broadcast mechanism. Processor/Cache directory logic provide responses to requests depending on the values of the directional bits.

Abstract: A cache coherency protocol uses a “Tagged” coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars.

Abstract: A data processing system includes a plurality of nodes, which each contain at least one agent, and data storage accessible to agents within the nodes. The plurality of nodes are coupled by a non-hierarchical interconnect including multiple non-blocking uni-directional address channels and at least one uni-directional data channel. The agents, which are each coupled to and snoop transactions on all of the plurality of address channels, can only issue transactions on an associated address channel. The uni-directional channels employed by the present non-hierarchical interconnect architecture permit high frequency pumped operation not possible with conventional bi-directional shared system buses. In addition, access latencies to remote (cache or main) memory incurred following local cache misses are greatly reduced as compared with conventional hierarchical systems because of the absence of inter-level (e.g., bus acquisition) communication latency.

Abstract: According to a first aspect of the present invention, a data processing system is provided that includes a communication network to which multiple devices are coupled. A first of the multiple devices includes a number of requestors (or queues), which are each permanently assigned a respective one of a number of unique tags. In response to a communication request by a requestor within the first device, a tag assigned to the requestor is transmitted on the communication network in conjunction with the requested communication transaction. According to a second aspect of the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication.