Abstract: Examples of bandgap circuits and elements thereof enable generation of an accurate and stable bandgap reference voltage that is not affected by low current gain. An example circuit includes first and second input transistors, each having an emitter to receive a tail current; first and second core transistors, a collector of each coupled to ground; a first lower leg coupled between a first upper leg and the emitter of the first core transistor at a first current input coupled to the base of the first input transistor; a second lower leg coupled between a second upper leg and the emitter of the second core transistor at a second current input coupled to the base of the second input transistor; and a base resistor coupled between the base and collector of the first core transistor. The input transistor pair has a current density ratio that is the same as that of the core transistor pair.

Abstract: Examples of bandgap circuits and elements thereof enable generation of an accurate and stable bandgap reference voltage that is not affected by low current gain. An example circuit includes first and second input transistors, each having an emitter to receive a tail current; first and second core transistors, a collector of each coupled to ground; a first lower leg coupled between a first upper leg and the emitter of the first core transistor at a first current input coupled to the base of the first input transistor; a second lower leg coupled between a second upper leg and the emitter of the second core transistor at a second current input coupled to the base of the second input transistor; and a base resistor coupled between the base and collector of the first core transistor. The input transistor pair has a current density ratio that is the same as that of the core transistor pair.

Abstract: An example apparatus includes: An amplifier comprising folded cascode circuitry having an input and an output, an input pair coupled to the input, clamp circuitry including: a first transistor having a first drain, a first source, and a first gate, the first source coupled to the output, a second transistor having a second drain, a second source, and a second gate, the second drain coupled to the first drain and the second gate coupled to the first drain and second drain, a third transistor having a third drain, a third source, and a third gate, the third source coupled to the output, and a fourth transistor having a fourth drain, a fourth source, and a fourth gate, the fourth drain coupled to the third drain and the fourth gate coupled to the third drain and the fourth drain.

Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.

Abstract: The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data input signal; a combinational logic circuit for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal; a first multiplexer for providing a clock signal to the more than two flip/flops during a test mode; a second multiplexer for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit, and for providing a scan data output signal; and wherein the scan data input signal and the scan data output signal share an input/output pin.

Abstract: A gamma reference voltage generator (10B) for an LCD display includes a control interface logic circuit (48) having an output bus coupled to inputs of a first register (46) having outputs coupled to inputs of a second register (42) the outputs of which are coupled to corresponding inputs of plurality of DACs (28). The control interface logic circuit receives gray scale codes representative of gamma reference voltages and transfers the codes via the output bus into the first register and controls further transfer of the codes to inputs of the DACs to instantaneously or rapidly update gamma correction voltages applied to the LCD display.

Abstract: A segmented string digital-to-analog converter (DAC) comprises least significant bits (LSB subword) interpolation circuitry. The LSB subword interpolation circuitry defines, for each input digital word (or code), an offset voltage representative of an M bit LSB subword of the input digital word. The offset voltage modifies a coarse analog representation voltage of an N bit most significant bits (MSB subword) of the input digital word. The LSB subword interpolation circuitry includes a coarse analog representative voltage input, an LSB subword input, an LSB modification circuit, an offset voltage defining circuit, and a summation device. The DAC further includes a segmented string and a coarse level device connected to tap points of the segmented string. The offset voltage defining circuit receives an LSB subword and defines an offset voltage for modifying the corresponding coarse analog representative voltage. Such an offset voltage is defined based on a given modified LSB subword.