Abstract: A programmable state counter generates an output signal when a predetermined count sequence matches a programmed input data pattern. A synchronous maximal length shift counter generates 2.sup.N -1 unique output states as a predetermined count sequence. A string of first flipflops receive the programmed input data pattern at first data input and the predetermined count sequence at second data inputs. The first and second data inputs of first flipflops are combined as a logical exclusive-NOR operation. A second flipflop has a first data input wired-OR'ed to inverted outputs of a first portion of the first flipflops, and a second data input wired-OR'ed to the inverted outputs of a second portion of the first flipflops. The first and second data inputs of the second flipflop are combined as a logical OR operation for providing the output signal of the programmable state counter.

Abstract: An integrated circuit package having a low reflection input pin comprising a high frequency signal conductor internal to the semiconductor package is provided by coupling a first input pin to a second input pin with a conductive path, the conductive path having a constant characteristic impedance which matches the characteristic impedance of an external signal line which is coupled to the first input pin. A portion of the conductive path forms a bonding pad using for wire bonding, or other bonding technique, between the conductive path and a bonding pad of the integrated circuit. In this manner the impedance mismatch between an external signal conductor and the integrated circuit bonding pad is eliminated, and the total impedance mismatch between the semiconductor package and the external signal line is greatly reduced, resulting in higher frequency operation of the integrated circuit.

Abstract: A bidirectional switching circuit is provided for testing a large number of AC data paths of LSI macrocell arrays. The circuit includes a plurality of bidirectional pins, a first logic means, and a second logic means. The switching circuit may be used to deskew a general purpose LSI tester wherein any pin may be used for input or output and the pulse at any pin may be inverted. The second logic means, receiving signals on selected pins, initializes the first logic means thereby determining which pins may be used for testing the data path desired.

Abstract: This relates to an expandable arithmetic logic unit (ALU) capable of performing binary and BCD addition and subtraction and various logic transfer functions in no more than four stages of logic delay from data input to ALU output. Propagate and generate signals (Pi and Gi) are produced in a single stage of delay and are applied to group propagate and generate logic. The group propagate and group generate signals are produced in a second stage of logic delay and are utilized to form carry look-ahead signals in a third stage of logic delay. Additional logic produces the required logic transfer signals (Hi) one logic delay after generation of the individual Pi and Gi terms. The carry look-ahead signals and logic transfer signals are combined to produce the ALU output.

Abstract: A control memory address generation device, for use as a single device or in a slice environment, performs logical and/or data path selection functions with respect to control information from an arithmetic and logic unit or a control word field, or both, to generate the next control memory address. A flexible register organization and extender bus logic allows subroutining control, instruction or subroutine repetition, masking, branching (conditional or unconditional), and other address-related operations.

Abstract: A versatile programmable multi-bit shifter is provided which can be built on a single monolithic integrated circuit. The shifter is capable of performing arithmetic shift left, arithmetic shift right, rotate left, rotate right, shifting right using two's complement, shifting left using two's complement, forcing the output to a predetermined logic level, or placing a sign bit at all the outputs. The programmable multi-bit shifter comprises an input data multiplexer for receiving input data and an output multiplexer coupled to the input multiplexer. The output multiplexer provides the data output for the shifter. A decoder is also provided for decoding shift function inputs. A second decoder is provided for decoding scale factor shift inputs. Outputs of the second decoder are coupled to the input data multiplexer and to the output data multiplexer and also to a sign select logic circuitry. The sign select logic circuitry combines inputs from both decoders to control operation of the output multiplexer.

Abstract: A high speed digital data shifter capable of processing a plurality of parallel data bits and comprising a plurality of programmable data shifters arranged in an array. The plurality of programmable data shifters each have shift function select inputs, scale factor inputs, and a sign bit input and are capable of shifting data right, shifting data left, rotating data right, rotating data left, shifting using two's complements, and forcing the output to a predetermined logic level. The high speed array is capable of shifting data and of rotating data right and left. A plurality of scale factor terminals are provided for receiving scale factor commands. The scale factor terminals are coupled to the programmable data shifters for controlling the number of positions that data is shifted by each programmable data shifter. A plurality of logic gates receive and decode shift select function commands.