Patents by Inventor Jerry Fox

Jerry Fox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12460480
    Abstract: A hook support device having a longitudinal plate with a top surface, a front side, a first end, and a second end opposite the first end. The first end has a first hook, the second end has a second hook, and the front side has a third hook. The top surface of the longitudinal plate is constructed to contact an outer surface of a side rail of a ladder. The first hook and second hook are mounted on the outer surface of the side rail. The third hook is constructed to simultaneously i) contact a front surface of the side rail, ii) hook the hook support device to the front surface and outer surface, and iii) prevent the hook support device from sliding down the side rail. The hooks do not interfere with the use of the steps or rungs of the ladder.
    Type: Grant
    Filed: June 4, 2025
    Date of Patent: November 4, 2025
    Inventor: Jerry Fox
  • Patent number: 7915931
    Abstract: A power sequencing circuit includes a PNP transistor, a first, second and third resistor, and a logic enabled regulator. A voltage is coupled at a first node to the emitter of the transistor, the first resistor is coupled between the first node and the base of the transistor, the second resistor is coupled between the base and a grounded node, the third resistor is coupled between the grounded node and the collector of the transistor, and the logic enabled regulator has an enable pin coupled to and driven by the collector.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: March 29, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jerry Fox, Paul D Young
  • Publication number: 20100188123
    Abstract: A power sequencing circuit includes a PNP transistor, a first, second and third resistor, and a logic enabled regulator. A voltage is coupled at a first node to the emitter of the transistor, the first resistor is coupled between the first node and the base of the transistor, the second resistor is coupled between the base and a grounded node, the third resistor is coupled between the grounded node and the collector of the transistor, and the logic enabled regulator has an enable pin coupled to and driven by the collector.
    Type: Application
    Filed: January 29, 2009
    Publication date: July 29, 2010
    Inventors: Jerry Fox, Paul D. Young