Patents by Inventor Jerry G. Fossum

Jerry G. Fossum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Floating-body/gate DRAM cell
    Patent number: 8787072
    Abstract: Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated diode is used to drive the gate of a second transistor structure of a cell. In another embodiment, a body-tied-source (BTS) field effect transistor is used to drive the gate of the second transistor structure of a cell.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: July 22, 2014
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Jerry G. Fossum, Zhichao Lu
  • Two-transistor floating-body dynamic memory cell
    Patent number: 8498140
    Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: July 30, 2013
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Jerry G. Fossum, Leo Mathew, Michael Sadd, Vishal P. Trivedi
  • FLOATING-BODY/GATE DRAM CELL
    Publication number: 20110222337
    Abstract: Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated diode is used to drive the gate of a second transistor structure of a cell. In another embodiment, a body-tied-source (BTS) field effect transistor is used to drive the gate of the second transistor structure of a cell.
    Type: Application
    Filed: December 29, 2009
    Publication date: September 15, 2011
    Applicant: University of Florida Research Foundation, Inc.
    Inventors: Jerry G. Fossum, Zhichao Lu
  • Two-Transistor Floating-Body Dynamic Memory Cell
    Publication number: 20100329043
    Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.
    Type: Application
    Filed: October 1, 2008
    Publication date: December 30, 2010
    Applicant: University of Florida Research Foundation, Inc.
    Inventors: Jerry G. Fossum, Leo Mathew, Michael Sadd, Vishal P. Trivedi
  • Hybrid-FET and its application as SRAM
    Patent number: 7470951
    Abstract: A semiconductor device (51) is provided herein. The semiconductor device comprises (a) a substrate (57), a semiconductor layer (53) disposed on said substrate and comprising a horizontal region (54) and a fin which extends above, and is disposed adjacent to, said horizontal region, and (c) at least one channel region (63) defined in said fin and in said horizontal region.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: December 30, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Jerry G. Fossum
  • Body-tied-to-body SOI CMOS inverter circuit
    Patent number: 6630376
    Abstract: An SOI CMOS inverter circuit in which a silicide layer in combination with body tie regions tie a p-type body region and an n-type body region together. At the same time, however, the body regions remain floating electrically so that the benefits of SOI are maintained. The silicide layer permits excess carriers to be recombined via the respective body regions so that the body region potential does not get modulated by generation/recombination effects. Thus, a hysteresis effect in the inverter circuit will be reduced.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: October 7, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srinath Krishnan, Jerry G. Fossum, Meng-Hsueh Chiang
  • Body-tied-to-body SOI CMOS inverter circuit
    Patent number: 6498371
    Abstract: An SOI CMOS inverter circuit in which a silicide layer in combination with body tie regions tie a p-type body region and an n-type body region together. At the same time, however, the body regions remain floating electrically so that the benefits of SOI are maintained. The silicide layer permits excess carriers to be recombined via the respective body regions so that the body region potential does not get modulated by generation/recombination effects. Thus, a hysteresis effect in the inverter circuit will be reduced.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: December 24, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srinath Krishnan, Jerry G. Fossum, Meng-Hsueh Chiang
  • Oxide charge induced high low junction emitter solar cell
    Patent number: 4483063
    Abstract: A method of forming a high-low junction emitter silicon solar cell including the producing of an electron accumulation layer by oxide-charge-induction.
    Type: Grant
    Filed: June 1, 1982
    Date of Patent: November 20, 1984
    Assignee: University of Florida
    Inventors: Arnost Neugroschel, Shing-Chong Pao, Fred A. Lindholm, Jerry G. Fossum, Chih-Tang Sah
  • Oxide charge induced high low junction emitter solar cell
    Patent number: 4343962
    Abstract: A high-low junction emitter silicon solar cell including an electron accumulation layer formed by oxide-charge-induction.
    Type: Grant
    Filed: February 2, 1981
    Date of Patent: August 10, 1982
    Inventors: Arnost Neugroschel, Shing-Chong Pao, Fred A. Lindholm, Jerry G. Fossum, Chin-Tang Sah