Patents by Inventor Jerry Gray

Jerry Gray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6639569
    Abstract: An integrated heads-up display (HUD) and cluster projection panel assembly for a motor vehicle includes a housing and a display unit contained within the housing. The display unit has first and second pixel arrays which turn on and off for forming first and second image light beams in response to receiving light. A HUD unit is contained within the housing. The HUD unit has a first converter for transmitting light to the first pixel array of the display unit. The HUD unit further has a first projection optic for projecting the first image light beam from the first pixel array of the display unit onto a windscreen of the motor vehicle. A cluster projection panel unit is contained within the housing. The cluster projection panel has a second converter for transmitting light to the second pixel array of the display unit.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: October 28, 2003
    Assignee: Ford Global Technologies, LLC
    Inventors: Jerry Gray Kearns, Mahendra Somasara Dassanayake, Terry Thomas Cwik
  • Patent number: 5173621
    Abstract: Circuit configurations are described for use with split lead leadframes and relatively isolated quiet and noisy power rails to reduce power rail noise and circuit noise. An octal register transceiver circuit incorporates a latch (300) coupled to relatively quiet power rails (42,44) and an output buffer circuit (400) having an input circuit coupled to the latch (300) and relatively quiet power rails (42,44). The output driver transistors (Q433,Q434) of the output buffer circuit (400) are coupled to the relatively noisy output power rails (52,54) to isolate the latch circuit from power rail noise and minimize erroneous operation of the latch. A DC Miller Killer circuit (450) is constructed with delay control components (D456,D457,R460) and an alternative discharge path (R458,D459) to reduce aggravation of power rail noise during operation of DCMK.
    Type: Grant
    Filed: July 12, 1991
    Date of Patent: December 22, 1992
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Dana Fraser, Ray A. Mentzer, Jerry Gray, Geoff Hannington, Susan M. Keown, Gaetan L. Mathieu
  • Patent number: 5065224
    Abstract: To reduce the effect of on-chip power rail perturbation on integrated circuit performance, a lead configuration is provided having two or more leads originating at a single terminal, e.g. a pin. While merged near the pin in a common segment, the leads connect on the integrated circuit chip to respective isolated internal rails of the same type serving respective device stages. Preferably, the inductance of the common segment is minimized. In accordance with the invention, an octal registered transceiver is provided with isolated V.sub.cc and ground rails for the latch and output buffers. The lead configuration described above is used for both V.sub.cc and ground. Several circuits are improved to optimize performance of the device, including a DC Miller killer circuit. Also in accordance with the invention, the paddle of a PDIP leadframe is supported by tiebars that extends to the dambars at the sides of the leadframe.
    Type: Grant
    Filed: September 8, 1988
    Date of Patent: November 12, 1991
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Dana Fraser, Ray A. Mentzer, Jerry Gray, Geoff Hannington, Susan M. Keown, Gaetan L. Mathieu