Abstract: Systems, methods, and apparatuses are disclosed herein for aggregating packets and transmitting the aggregated packets to a device in an integrated circuit. These systems, methods, and apparatuses may include receiving, at a buffer of a System-on-Chip (“SoC”), a plurality of packets for output. The SoC may determine, when each packet of the plurality of output packets is received, whether the buffer has reached a predetermined capacity. In response to determining that the buffer has reached the predetermined capacity, the SoC may identify a subset of packets of the plurality of packets that share a common characteristic, may aggregate the subset into a jumbo packet, and may transmit the jumbo packet to a destination SoC.

Abstract: Systems, methods, and apparatuses are disclosed herein for discovering unknown chips and chip components of a MoChi system. To this end, a first System-on-Chip (“SoC”) may transmit a first discovery packet from a downlink MoChi port the first SoC to an uplink MoChi port of a second SoC. The first SoC may receive, at the downlink MoChi port of the first SoC, from the uplink MoChi port of the second SoC, a first reply packet. The first SoC may determine whether the reply packet indicates that the second SoC is a known SoC or an unknown SoC. In response to determining that the second SoC is an unknown SoC, the first SoC may assign a first address mask to the first SoC that identifies that the second SoC can be reached by way of the first SoC.

Abstract: Systems, methods, and apparatuses are disclosed herein for identifying a topology of a MoChi system prior to a boot-up of an operating system. A master SoC may detect, prior to boot-up of an operating system that uses the master SoC, an initialization command, and may, in response to detecting the initialization command, assign a first chip identifier to the master SoC. The master SoC may transmit a discovery communication from the master SoC to a slave SoC that is one hop away from the master SoC. The slave SoC may determine whether the slave SoC is a last hop SoC, and, in response to determining that the slave SoC is a last hop SoC, the slave SoC may transmit a reply communication to the master SoC. The master SoC may then assign, based on the reply communication, a second chip identifier to the slave SoC.

Abstract: Systems and methods for transmitting a group of interrupts across nodes are provided. A first interrupt signal, comprising a first group of interrupts, is received, with a first node, from a second node. A second interrupt signal, comprising a second group of interrupts, is received, from storage circuitry of the first node, the second interrupt signal represents an interrupt signal received prior to the first interrupt signal. The first interrupt signal is combined with the second interrupt signal using a function to generate a combined interrupt signal. The second interrupt signal is compared to the combined interrupt signal to detect a change in a first bit position of the second interrupt signal. In response to detecting that the first bit position has changed to become asserted, an interrupt process corresponding to the first bit position is performed. The combined signal is stored in place of the second interrupt signal.

Abstract: Comparison circuitry includes a first memory that stores a list of data items, a second memory that stores a list of most-recently used ones of the data items, a first comparator that compares an input data item first to the ones of the data items in the second memory and, only in absence of a hit in the second memory, compares the input data item to the data items in the first memory. At least one additional comparator may operate in parallel with the first comparator to compare the input data item to respective data items in at least one additional second memory, and to compare the input data item to respective data items in the first memory in absence of a respective hit in the at least one additional second memory. A data communications system may include a decoder incorporating such comparison circuitry.

Abstract: Systems and methods for transmitting a group of interrupts across nodes are provided. A first interrupt signal, comprising a first group of interrupts, is received, with a first node, from a second node. A second interrupt signal, comprising a second group of interrupts, is received, from storage circuitry of the first node, the second interrupt signal represents an interrupt signal received prior to the first interrupt signal. The first interrupt signal is combined with the second interrupt signal using a function to generate a combined interrupt signal. The second interrupt signal is compared to the combined interrupt signal to detect a change in a first bit position of the second interrupt signal. In response to detecting that the first bit position has changed to become asserted, an interrupt process corresponding to the first bit position is performed. The combined signal is stored in place of the second interrupt signal.

Abstract: Systems, methods, and apparatuses are disclosed herein for identifying a topology of a MoChi system prior to a boot-up of an operating system. A master SoC may detect, prior to boot-up of an operating system that uses the master SoC, an initialization command, and may, in response to detecting the initialization command, assign a first chip identifier to the master SoC. The master SoC may transmit a discovery communication from the master SoC to a slave SoC that is one hop away from the master SoC. The slave SoC may determine whether the slave SoC is a last hop SoC, and, in response to determining that the slave SoC is a last hop SoC, the slave SoC may transmit a reply communication to the master SoC. The master SoC may then assign, based on the reply communication, a second chip identifier to the slave SoC.

Abstract: Systems, methods, and apparatuses are disclosed herein for aggregating packets and transmitting the aggregated packets to a device in an integrated circuit. These systems, methods, and apparatuses may include receiving, at a buffer of a System-on-Chip (“SoC”), a plurality of packets for output. The SoC may determine, when each packet of the plurality of output packets is received, whether the buffer has reached a predetermined capacity. In response to determining that the buffer has reached the predetermined capacity, the SoC may identify a subset of packets of the plurality of packets that share a common characteristic, may aggregate the subset into a jumbo packet, and may transmit the jumbo packet to a destination SoC.

Abstract: Comparison circuitry includes a first memory that stores a list of data items, a second memory that stores a list of most-recently used ones of the data items, a first comparator that compares an input data item first to the ones of the data items in the second memory and, only in absence of a hit in the second memory, compares the input data item to the data items in the first memory. At least one additional comparator may operate in parallel with the first comparator to compare the input data item to respective data items in at least one additional second memory, and to compare the input data item to respective data items in the first memory in absence of a respective hit in the at least one additional second memory. A data communications system may include a decoder incorporating such comparison circuitry.

Abstract: Systems, methods, and apparatuses are disclosed herein for discovering unknown chips and chip components of a MoChi system. To this end, a first System-on-Chip (“SoC”) may transmit a first discovery packet from a downlink MoChi port the first SoC to an uplink MoChi port of a second SoC. The first SoC may receive, at the downlink MoChi port of the first SoC, from the uplink MoChi port of the second SoC, a first reply packet. The first SoC may determine whether the reply packet indicates that the second SoC is a known SoC or an unknown SoC. In response to determining that the second SoC is an unknown SoC, the first SoC may assign a first address mask to the first SoC that identifies that the second SoC can be reached by way of the first SoC.