Patents by Inventor Jerry K. Tanaka

Jerry K. Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit memory having column redundancy with no timing penalty
    Patent number: 6366508
    Abstract: A memory array includes a zone of memory elements and a column multiplexer. The zone of memory elements is arranged in rows and columns, including a set of non-redundant columns and a redundant column. The column multiplexer has a section coupled to the set of non-redundant columns and to the redundant column. The column multiplexer has a selectable non-redundant path through the section for each of the non-redundant columns and a selectable redundant path for the redundant column. The redundant path is interchangeable with any one of the non-redundant paths.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: April 2, 2002
    Assignee: LSI Logic Corporation
    Inventors: Ghasi R. Agrawal, Jerry K. Tanaka