Patents by Inventor Jerry Kao
Jerry Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11748546Abstract: A system includes a substrate having a first side and a second side opposite the first side, a cell on the substrate having a first pin on either the first side or the second side, and a second pin on the second side, a first signal connected to the first pin, and a second signal connected to the second pin.Type: GrantFiled: July 1, 2022Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LIMITEDInventors: Sheng-Hsiung Chen, Jerry Kao, Kuo-Nan Yang, Jack Liu
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Publication number: 20220335194Abstract: A system includes a substrate having a first side and a second side opposite the first side, a cell on the substrate having a first pin on either the first side or the second side, and a second pin on the second side, a first signal connected to the first pin, and a second signal connected to the second pin.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, LimitedInventors: Sheng-Hsiung Chen, Jerry Kao, Kuo-Nan Yang, Jack Liu
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Patent number: 9311440Abstract: A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.Type: GrantFiled: May 10, 2012Date of Patent: April 12, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jerry Kao, King-Ho Tam, Meng-Xiang Lee, Li-Chung Hsu, Chi-Yeh Yu, Chung-Min Fu, Chung-Hsing Wang
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Publication number: 20130304449Abstract: A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.Type: ApplicationFiled: May 10, 2012Publication date: November 14, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jerry KAO, King-Ho TAM, Meng-Xiang LEE, Li-Chung HSU, Chi-Yeh YU, Chung-Min FU, Chung-Hsing WANG
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Patent number: 8289063Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.Type: GrantFiled: May 18, 2011Date of Patent: October 16, 2012Assignee: The Regents of the University of MichiganInventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
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Publication number: 20110215854Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.Type: ApplicationFiled: May 18, 2011Publication date: September 8, 2011Applicant: The Regents of the University of MichiganInventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
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Patent number: 7956664Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.Type: GrantFiled: December 3, 2007Date of Patent: June 7, 2011Assignee: The Regents of the University of MichiganInventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
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Patent number: 7719316Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry.Type: GrantFiled: December 3, 2007Date of Patent: May 18, 2010Assignee: The Regents of the University of MichiganInventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
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Patent number: 7719317Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal.Type: GrantFiled: December 3, 2007Date of Patent: May 18, 2010Assignee: The Regents of the University of MichiganInventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
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Publication number: 20080303576Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal.Type: ApplicationFiled: December 3, 2007Publication date: December 11, 2008Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
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Publication number: 20080303552Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry.Type: ApplicationFiled: December 3, 2007Publication date: December 11, 2008Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
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Publication number: 20080150605Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.Type: ApplicationFiled: December 3, 2007Publication date: June 26, 2008Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
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Publication number: 20070237012Abstract: A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.Type: ApplicationFiled: October 13, 2005Publication date: October 11, 2007Inventors: Jente Kuang, Jerry Kao, Hung Ngo, Kevin Nowka
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Publication number: 20070139082Abstract: A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.Type: ApplicationFiled: December 15, 2005Publication date: June 21, 2007Applicant: International Business Machines CorporationInventors: Jerry Kao, Chung-Tao Li, Salvatore Storino, Christophe Tretz