Patents by Inventor Jerry Kao

Jerry Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9311440
    Abstract: A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jerry Kao, King-Ho Tam, Meng-Xiang Lee, Li-Chung Hsu, Chi-Yeh Yu, Chung-Min Fu, Chung-Hsing Wang
  • Publication number: 20130304449
    Abstract: A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 14, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry KAO, King-Ho TAM, Meng-Xiang LEE, Li-Chung HSU, Chi-Yeh YU, Chung-Min FU, Chung-Hsing WANG
  • Patent number: 8289063
    Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: October 16, 2012
    Assignee: The Regents of the University of Michigan
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
  • Publication number: 20110215854
    Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.
    Type: Application
    Filed: May 18, 2011
    Publication date: September 8, 2011
    Applicant: The Regents of the University of Michigan
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
  • Patent number: 7956664
    Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: June 7, 2011
    Assignee: The Regents of the University of Michigan
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
  • Patent number: 7719317
    Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: May 18, 2010
    Assignee: The Regents of the University of Michigan
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
  • Patent number: 7719316
    Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: May 18, 2010
    Assignee: The Regents of the University of Michigan
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
  • Publication number: 20080303576
    Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal.
    Type: Application
    Filed: December 3, 2007
    Publication date: December 11, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
  • Publication number: 20080303552
    Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry.
    Type: Application
    Filed: December 3, 2007
    Publication date: December 11, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
  • Publication number: 20080150605
    Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.
    Type: Application
    Filed: December 3, 2007
    Publication date: June 26, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
  • Publication number: 20070237012
    Abstract: A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
    Type: Application
    Filed: October 13, 2005
    Publication date: October 11, 2007
    Inventors: Jente Kuang, Jerry Kao, Hung Ngo, Kevin Nowka
  • Publication number: 20070139082
    Abstract: A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.
    Type: Application
    Filed: December 15, 2005
    Publication date: June 21, 2007
    Applicant: International Business Machines Corporation
    Inventors: Jerry Kao, Chung-Tao Li, Salvatore Storino, Christophe Tretz