Abstract: Antenna structures and methods of operating the same are described. One apparatus includes a metal cover having a first corner ground element, a second corner ground element, a first strip element, a second strip element, a radio frequency (RF) feed, and a RF circuit. The first strip element is physically separated from the first corner ground element by a first cutout in the metal cover. The first strip element is physically separated from the second strip element by a second cutout in the metal cover. The second strip element is physically separated from the second corner ground element by a third cutout in the metal cover. The RF circuitry is coupled to the RF feed, where the RF circuitry is operable to cause the first corner ground element and the first strip element as well as the second corner ground element and the second strip element to radiate electromagnetic energy.

Abstract: A system and method for coding identification in a wireless transmit and receive protocol for single-frequency peripheral devices. A wireless system, consisting of a first data transmitting unit, a second data transmitting unit, and a data receiving unit, is able to send a packet twice using an Amplitude-Shift Keying (ASK) Modulation technique, repeated sending, and a single frequency, during one packet transmission. In order to lower the cost of the wireless module, the length of a packet transmission period is to be four times the sum of the time required to send two separate packets, thus allowing simultaneous control of two data transmitting units, and recognition of two different packets using a single data receiving unit.

Abstract: An architecture for data retrieval from a plurality of coupling queues. At least first and second data queues are provided for receiving data thereinto. The data is read from the at least first and second data queues with reading logic, the reading logic reading the data according to a predetermined queue selection algorithm. The data read from by reading logic and forwarded to an output queue.

Abstract: A burglarproof and event-recording apparatus for a vehicle comprises at least one camera arranged on the vehicle to surveil an environmental image for the vehicle and store the image to an image-storing and logic-controlling unit until an alarm flag is set to 1 by the image-storing and logic-controlling unit. The apparatus will raise alarm and set the alarm flag to 1 once the vehicle is intruded. At this time, the image is stored in a currently-used memory block of the image-storing and logic-controlling unit and the intrusion condition is formed to the vehicle owner.

Abstract: A burglarproof and event-recording apparatus for a vehicle comprises at least one camera arranged on the vehicle to surveil an environmental image for the vehicle and store the image to an image-storing and logic-controlling unit until an alarm flag is set to 1 by the image-storing and logic-controlling unit. The apparatus will raise alarm and set the alarm flag to 1 once the vehicle is intruded. At this time, the image is stored in a currently-used memory block of the image-storing and logic-controlling unit and the intrusion condition is formed to the vehicle owner.

Abstract: A system and method for coding identification in a wireless transmit and receive protocol for single-frequency peripheral devices. A wireless system, consisting of a first data transmitting unit, a second data transmitting unit, and a data receiving unit, is able to send a packet twice using an Amplitude-Shift Keying (ASK) Modulation technique, repeated sending, and a single frequency, during one packet transmission. In order to lower the cost of the wireless module, the length of a packet transmission period is to be four times the sum of the time required to send two separate packets, thus allowing simultaneous control of two data transmitting units, and recognition of two different packets using a single data receiving unit.

Abstract: A system for accumulating data relating to performance parameters of a data communication system is provided in order to determine average values of these parameters. The system comprises multiple registers used for calculating average values of particular performance parameters, such as bus latency, interrupt latency, receive service routine time, and receive frame copy time. Each of the registers contains an event counter and a timer. The event counter increments upon occurrence of an event relating to the performance parameter accumulated by the corresponding register. The timer is activated by the occurrence of the event, and increments at a predetermined rate until the event comes to an end. The timer resumes incrementing when the next event occurs. As a result, the CPU is enabled to determine an average value of a particular parameter per an event relating to this parameter.

Abstract: A universal interface for communicating information to a proprietary physical interface. At least one output module is provided for transmitting information and an input module is provided for receiving the information. The output module and the input module are configured according to communication parameters of a predetermined type of physical interface to which the output module and the input module interface such that communication of the information is facilitated therebetween.

Abstract: An architecture for data retrieval from a plurality of coupling queues. At least first and second data queues are provided for receiving data thereinto. The data is read from the at least first and second data queues with reading logic, the reading logic reading the data according to a predetermined queue selection algorithm. The data read from by reading logic and forwarded to an output queue.

Abstract: A communication interface for processing errors between network devices. The communication interface includes an output interface of a first network device for generating output control information and parity information of output information transmitted therefrom, and an error-handling interface of a second network device, which error-handling interface is in operative communication with the output interface to process the output control information and the parity information of the output information by, checking parity of the parity information of the output information received from the first network device, terminating the output information when an error in the parity is detected, and recovering a boundary of the output information when an error in the output control information is detected.

Abstract: A system for freezing a communication device in a debug mode has a clock control circuit arranged to produce an internal clock signal in response to an external clock signal. When a stop signal is asserted, the internal clock signal is fixed in its off state. As a result, operations of internal registers supplied with the internal clock signal freeze in a chosen state. A scan test may be performed to examine the internal registers in the chosen state. A bypass clock signal is supplied to control the internal clock signal so as to move the internal registers from one state to another. Thus, an event that causes an error may be recreated.

Abstract: Data communications device and method for arbitrating access to a system memory of the communications device via a peripheral component interconnect (PCI) bus in a network interface having a memory management unit for managing transmit data transfers from the system memory to a transmit buffer memory, and receive data transfers from a receive buffer memory to the system memory. The memory management unit includes an arbitration block having an arbiter state machine, which receives requests for access to the PCI bus in order to provide the transmission and reception of data, descriptors and status information. The arbiter state machine grants the PCI bus access to a request having a higher priority in accordance with a preset priority scheme.

Abstract: An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending requests from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.

Abstract: A circuit and method for switching between different frequency clock domains that are out of phase. The circuit has a select input for selecting which frequency domain is to be output, a first circuit associated with the first clock domain, and a second circuit associated with the second clock domain. The first and second circuits are responsive to the select input and work together to disengage the first clock before the second clock is engaged.