Patents by Inventor Jerry Lee Doorenbos
Jerry Lee Doorenbos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881825Abstract: Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.Type: GrantFiled: December 29, 2020Date of Patent: January 23, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vadim Valerievich Ivanov, Munaf Hussain Shaik, Srinivas Kumar Pulijala, Patrick Forster, Jerry Lee Doorenbos
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Publication number: 20220360239Abstract: Disclosed is a system comprising a plurality of operational amplifiers, each operational amplifier having individually adjustable operational parameters, and a trimming circuit. The trimming circuit includes successive approximation register (SAR) logic that determines associated memory values. The trimming circuit changes the adjustable operational parameters of each operation amplifier based on the associated memory values.Type: ApplicationFiled: May 4, 2021Publication date: November 10, 2022Inventors: Vadim Valerievich Ivanov, Munaf Hussain Shaik, Srinivas Kumar Pulijala, Patrick Forster, Jerry Lee Doorenbos
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Publication number: 20220209730Abstract: Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Inventors: Vadim Valerievich Ivanov, Munaf Hussain Shaik, Srinivas Kumar Pulijala, Patrick Forster, Jerry Lee Doorenbos
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Patent number: 10848175Abstract: In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.Type: GrantFiled: September 9, 2019Date of Patent: November 24, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jerry Lee Doorenbos, Keith Eric Sanborn, Srikanth Vellore Avadhanam Ramamurthy, Mina Raymond Naguib Nashed, Dwight David Griffin
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Publication number: 20200007148Abstract: In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.Type: ApplicationFiled: September 9, 2019Publication date: January 2, 2020Inventors: Jerry Lee DOORENBOS, Keith Eric SANBORN, Srikanth VELLORE AVADHANAM RAMAMURTHY, Mina Raymond Naguib NASHED, Dwight David GRIFFIN
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Patent number: 10461771Abstract: In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.Type: GrantFiled: August 3, 2018Date of Patent: October 29, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jerry Lee Doorenbos, Keith Eric Sanborn, Srikanth Vellore Avadhanam Ramamurthy, Mina Raymond Naguib Nashed, Dwight David Griffin
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Publication number: 20190296764Abstract: In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.Type: ApplicationFiled: August 3, 2018Publication date: September 26, 2019Inventors: Jerry Lee DOORENBOS, Keith Eric SANBORN, Srikanth VELLORE AVADHANAM RAMAMURTHY, Mina Raymond Naguib NASHED, Dwight David GRIFFIN
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Patent number: 10305507Abstract: A first-order sigma-delta analog-to-digital converter includes an input terminal, an integrator circuit, a comparator, and control circuitry. The input terminal is configured to receive a unipolar input signal to be digitized. The integrator circuit is coupled to the input terminal. The comparator is coupled to an output of the integrator circuit. The control circuitry is coupled to the integrator circuit and the comparator. The control circuitry is configured to equalize time that an output signal generated by the integrator circuit is greater than zero and time that the output signal generated by the integrator circuit is less than zero during digitization of the unipolar input signal.Type: GrantFiled: May 17, 2018Date of Patent: May 28, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jerry Lee Doorenbos, Keith Eric Sanborn, Mina Raymond Naguib Nashed, Srikanth Vellore Avadhanam Ramamurthy, Dwight David Griffin
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Patent number: 9195341Abstract: Touch screen controllers and methods are presented for removing charger noise and other high frequency noise from touch screens in the presence of aliasing in which a digital low pass filter rejects the high frequency noise, a noise tracker determines whether noise is being aliased into the low pass filter pass band, and a noise shaper artificially induces or modifies aliasing in the system by adjusting an analog-to-digital converter sampling frequency and/or a panel scan frequency to try to move the aliased noise outside the low pass filter pass band.Type: GrantFiled: February 14, 2014Date of Patent: November 24, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Baboo Vikrhamsingh Gowreesunker, Ranga Seshu Paladugu, Jerry Lee Doorenbos
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Publication number: 20150234519Abstract: Touch screen controllers and methods are presented for removing charger noise and other high frequency noise from touch screens in the presence of aliasing in which a digital low pass filter rejects the high frequency noise, a noise tracker determines whether noise is being aliased into the low pass filter pass band, and a noise shaper artificially induces or modifies aliasing in the system by adjusting an analog-to-digital converter sampling frequency and/or a panel scan frequency to try to move the aliased noise outside the low pass filter pass band.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Applicant: Texas Instruments IncorporatedInventors: Baboo Vikrhamsingh Gowreesunker, Ranga Seshu Paladugu, Jerry Lee Doorenbos