Abstract: A dual-metal-trench silicon carbide Schottky pinch rectifier having a plurality of trenches formed in an n-type SiC substrate, with a Schottky contact having a relatively low barrier height on a mesa defined between adjacent ones of the trenches, and a Schottky contact having a relatively high barrier height at the bottom of each trench. The same metal used for the Schottky contact in each trench is deposited over the Schottky contact on the mesa. A simplified fabrication process is disclosed in which the high barrier height metal is deposited over the low barrier height metal and then used as an etch mask for reactive ion etching of the trenches to produce a self-aligned low barrier contact.

Abstract: A light responsive device (10) has a body (12) that includes a matrix comprised of Group III-V material, the matrix having inclusions (14) comprised of a Group V material contained therein. The body is responsive to a presence of a light beam that has a spatially varying intensity for modifying in a corresponding spatially varying manner a distribution of trapped photoexcited charge carriers within the body. The distribution of trapped charge carriers induces a corresponding spatial variation in at least one optical property of the Group III-V material, such as the index of refraction of the Group III-V material and/or an absorption coefficient of the Group III-V material. The Group III-V material is comprised of LTG GaAs:As or LTG AlGaAs:As.

Abstract: A doped or undoped photoresponsive material having metallic precipitates, and a PiN photodiode utilizing the material for detecting light having a wavelength of 1.3 micrometers. The PiN photodiode includes a substrate having a first compound semiconductor layer disposed thereon. The PiN photodiode further includes an optically responsive compound semiconductor layer disposed above the first compound semiconductor layer. The optically responsive layer includes a plurality of buried Schottky barriers, each of which is associated with an inclusion within a crystal lattice of a Group III-V material. The PiN device also includes a further compound semiconductor layer disposed above the optically responsive layer. For a transversely illuminated embodiment, waveguiding layers may also be disposed above and below the PiN structure. In one example the optically responsive layer is comprised of GaAs:As.

Abstract: A doped or undoped photoresponsive material having metallic precipitates, and a PiN photodiode utilizing the material for detecting light having a wavelength of 1.3 micrometers. The PiN photodiode includes a substrate having a first compound semiconductor layer disposed thereon. The PiN photodiode further includes an optically responsive compound semiconductor layer disposed above the first compound semiconductor layer. The optically responsive layer includes a plurality of buried Schottky barriers, each of which is associated with an inclusion within a crystal lattice of a Group III-V material. The PiN device also includes a further compound semiconductor layer disposed above the optically responsive layer. For a transversely illuminated embodiment, waveguiding layers may also be disposed above and below the PiN structure. In one example the optically responsive layer is comprised of GaAs:As.

Abstract: Heterostructures having a large lattice mismatch between an upper epilayer and a substrate and a method of forming such structures having a thin intermediate layer are disclosed. The strain due to a lattice mismatch between the intermediate layer and the substrate is partially relieved by the formation of edge type dislocations which are localized and photoelectrically inactive. Growth of the intermediate layer is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer is then grown in an unstrained and defect-free condition upon the intermediate layer where the unstrained lattice constant of the epilayer is about the same as the partially relieved strain lattice constant or the intermediate layer. An unstrained defect-free epilayer of InGaAs has been grown on a GaAs substrate with an intermediate layer 3-10 nm in thickness of InAs.

Abstract: Resonant tunneling devices having improved peak-to-valley current ratios are disclosed. The resonant tunneling device comprises a quantum well layer surrounded by first and second barrier layers, the first and second barrier layers being comprised of an indirect first III-V compound semiconductor. The first barrier layer being formed on a substrate of a second III-V compound semiconductor having a lattice constant larger than the lattice constant of the first barrier layer thereby inducing a biaxial stress in the first barrier layer. The biaxial stress results in an energy shift at resonance that increases the peak to valley current ratio of the device.

Abstract: A long wavelength detector is formed by coupling a highly doped cathode to an anode through an undoped quantum well or superlattice filter structure. The absorption mechanism is free-carrier absorption in a heavily doped direct bandgap semiconductor (the cathode). The cathode material is preferably chosen such that the conduction band edge is lower than the conduction band edge of the material forming the well of the resonant-tunneling filter. The cathode material should also be semiconductor material of relatively narrow direct bandgap with low effective electron mass. The detector device is biased so that electrons pass through the filter structure by resonant tunneling. To stimulate conduction, incident radiation must have a frequency (i.e., photon energy) sufficient to boost the energy of the cathode electrons from the Fermi energy level of the cathode to the resonance energy level of the quantum-well filter.

Abstract: The control of barriers to carrier flow in a contact between a metal and a higher band gap semiconductor employing an intermediate lower band gap semiconductor with doping and greater than 1.5% lattice mismatch. A WSi metal contact of doped InAs on GaAs of 7.times.10.sup.-6 ohm/cm.sup.2 is provided.This is a continuation application of pending prior application Ser. No. 183,473, filed on Apr. 15, 1988 now abandoned which is a continuation of Ser. No. 876,063, filed on June 14, 1986, now abandoned.

Abstract: A semiconductor device where an emitter material composition and doping profile produces an electron gas in a base adjacent a band offset heterojunction interface, the electrons in the electron gas in the base are confined under bias by a low barrier and the ballistic carriers have their kinetic energy controlled to prevent intervalley scattering by an electrostatic barrier that under influence of bias provides an essentially level conduction band in the portion of the base adjacent the collector.

Abstract: Control of the Fermi level pinning problem and the production of flat band surface performance in compound semiconductors is achieved by providing a cationic oxide free of anionic species on the surface of the semiconductor for flat band performance and with a localized inclusion of some anionic species for barrier performance so that oxide and metal work function responsiveness is available in structure and performance in MOSFET, MESFET and different work function metal FET structures. A cationic gallium oxide is produced on GaAs by oxide growth during illumination and while being rinsed with oxygenated water. The oxidation is used to produce both anionic and cationic species while the rinsing process selectively removes all the anionic species.

Abstract: A method and structures are described for fabricating junctions having metal electrodes separated by polycrystalline barriers with arbitrarily-chosen but controlled barrier height and shape is accomplished by varying the composition and doping of polycrystalline multinary compound semiconductor materials in the barrier, hence varying the Fermi level pinning position such that the Fermi level is fixed and controlled at and everywhere in between the two metal-insulator interfaces. It is known that Schottky barrier heights at metal/compound semiconductor interfaces are determined by a Fermi level pinning mechanism rather than by the electronic properties of the applied metallurgy. The present invention exploits the knowledge that the same type of Fermi level pinning occurs at semiconductor dislocations and grain boundaries. The present invention uses polycrystalline compound semiconductor alloys in which the pinning position is varied over a large range in metal/semiconductor structures.

Abstract: Submicron structure fabrication is accomplished by providing vapor chemical erosion of a compound crystal by suppressing the more volatile elements so that the less volatile element is provided with an anti-agglomeration and erosion rate limiting capability which can be followed by subsequent regrowth in the same environment. The erosion is sensitive to crystallographic orientation.

Abstract: A low band gap semiconductor heterostructure having a surface adaptable to planar processing and all semiconductor properties supported by a fabrication constraint relaxing substrate that does not provide a low impedance parallel current path. A superconductor normal superconductor device of n-InAs-100 nanometers thick with niobium superconductor electrodes spaced 250 nanometers apart and a 100 nanometer gate in the space. The N-InAs is supported by an undoped GaAs layer on a semi-insulating GaAs substrate. A heterojunction field effect transistor device having a GaAlAs gate over a channel 100 nanometers thick on an undoped GaAs layer on a semi-insulating GaAs substrate.

Abstract: An environmental interface for a semiconductor electro-optical conversion device layer that is optically transparent, electrically conductive and chemically passivating, made of an elemental semiconductor with an indirect band gap>1 electron volt in a layer between 20 and 200 Angstroms thick. A GaAs covered by GaAlAs converter with a 100 Angstrom Si layer over the GaAlAs is illustrated.

Abstract: In a semiconductor device, a contact with low resistance to a III-V compound semiconductor substrate was fabricated using refractory materials and small amounts of indium as the contact material. The contact material was formed by depositing Mo, Ge and W with small amounts of In onto doped GaAs wafers. The contact resistance less than 1.0 ohm millimeter was obtained after annealing at 800.degree. C. and the resistance did not increase after subsequent prolonged annealing at 400.degree. C.

Abstract: Control of the Fermi level pinning problem and the production of flat band surface performance in compound semiconductors is achieved by providing a cationic oxide free of anionic species on the surface of the semiconductor for flat band performance and with a localized inclusion of some anionic species for barrier performance so that oxide and metal work function responsiveness is available in structure and performance in MOSFET, MESFET and different work function metal FET structures. A cationic gallium oxide is produced on GaAs by oxide growth during illumination and while being rinsed with oxygenated water. The oxidation is used to produce both anionic and cationic species while the rinsing process selectively removes all the anionic species.

Abstract: A surface termination of a compound semiconductor is provided wherein conditions are provided for a pristine surface to be retained in an unpinned condition and a surface layer of a non-metallic material is provided. A GaAs substrate is heated in an oxygen-free atmosphere at high temperature with hydrogen sulfide, producing a pristine surface with a coating of gallium sulfide covered with a 1,000 nanometer covering of low temperature plasma enhanced chemical vapor deposited silicon dioxide.

Abstract: A semiconductor photodetector is formed of interdigitated, metal-semiconductor-metal electrodes disposed on a surface of semi-insulating semiconductor material, gallium arsenide. Radiation such as infra-red or visible light is converted to an electric current flowing between the electrodes upon application of a bias voltage between the electrodes. A Schottky barrier at the junction of each electrode surface and the semiconductor surface limits current flow to that produced by photons. Tunneling of charge carriers of the current under the Schottky barrier, which tunneling results from the entrapment of charge carriers on the semiconductor surface, is inhibited by the production of a heterojunction surface layer upon the foregoing surface between the electrodes to repulse the charge carriers and prevent their entrapment at the surface. The heterojunction layer may be doped to enhance the repulsion of charge carriers.

Abstract: An ohmic contact to intermetallic semiconductors with a resistance of much less than 10.sup.-6 ohm cm.sup.2 can be provided by introducing between the semiconductor and an external metal contact an atomically compatible barrier-free graded layer of a conductor having at the interface with a metal external contact an energy gap width of the semiconductor less than 0.5 electron volts. An ohmic contact for gallium arsenide can be provided by a graded region of indium gallium arsenide that decreases to indium arsenide at the interface with a metal.

Abstract: An FET transistor is provided having a two element semiconductor channel region between metal contacts and epitaxial therewith a graded three element seminconductor, in which two of the three elements are in common with the semiconductor of the channel, positioned between a Schottky barrier gate of the same contact metal and the channel. An FET with a GaAs channel between tin source and drain contacts, a graded 500 to 1000 Angstrom thick GaAlAs region epitaxial with the channel and a Schottky barrier tin metal gate over the GaAlAs region.