Abstract: A non-volatile MOS memory cell which includes a bistable (flip-flop) circuit with slightly imbalanced loads. An electrically programmable, floating gate device is coupled across a portion of one of the loads to permit selective shunting. When the cell is powered-down (such as at power failure), the floating gate is either charged or discharged as a function of the state of the flip-flop. When power is reapplied, the imbalance caused by the selective shunting forces the flip-flop to its previous state. The relatively small cell does not require resetting, and the stored information is returned in its true (non-complementary) form when the cell is reactivated.

Abstract: An electrically programmable and electrically erasable MOS memory device suitable for high density integrated circuit memories is disclosed. Carriers are tunneled between a floating conductive gate and a doped region in the substrate to program and erase the device. A minimum area of thin oxide (70 A-200 A) is used to separate this doped region from the floating gate. In one embodiment, a second layer of polysilicon is used to protect the thin oxide region during certain processing steps.