Abstract: Improved performance for attenuated testing when probing a device under test with a probe array is provided. By moving the attenuation components from their conventional location on the printed circuit board of the probe head to the space transformer of the probe head, electrical path lengths can be decreased, thereby improving performance. This is particularly helpful in connection with loopback testing.

Abstract: Systems and methods for gray scale lithography for defining edges such as on microelectronic device patterns during integrated circuit fabrication are disclosed. Methods for critical dimension edge placement and slope enhancement utilize central pixel dose addition or modulated inner pixels. A method for gray scale lithography for defining edges of features generally comprises identifying a center pixel of a feature, exposing the general width of the feature including the identified center pixel with full doses, and enhancing the identified center pixel by exposing the identified center pixel with additional dose to accurately place the edge of the feature, whereby the edge of the feature is defined and moved by exposing the center pixel with the additional dose.

Abstract: A semiconductor fabrication gray level photolithography strategy, in which the energy beam intensities corresponding to each gray level are selected from a set of non-linear, non-monotonic intensities. Rasterized geometric shape edges are defined by associating one or more intermediate gray levels with pixels in at least one row of pixels. The geometric shape is printed or imaged on an energy sensitive layer by modulating an energy beam to the intensity corresponding to the associated gray level, and directing the modulated beam to the pixel location on the layer. The intensities corresponding to the gray levels are selected so as to optimize critical dimension (CD) characteristics and other printing features.

Abstract: Systems and methods for gray scale lithography for defining edges such as on microelectronic device patterns during integrated circuit fabrication are disclosed. Methods for critical dimension edge placement and slope enhancement utilize central pixel dose addition or modulated inner pixels. A method for gray scale lithography for defining edges of features generally comprises identifying a center pixel of a feature, exposing the general width of the feature including the identified center pixel with full doses, and enhancing the identified center pixel by exposing the identified center pixel with additional dose to accurately place the edge of the feature, whereby the edge of the feature is defined and moved by exposing the center pixel with the additional dose.

Abstract: An acousto-optic modulator for use with a multi-channel laser beam system, for instance, is of conventional structure except that two different RF (radio frequency) signals drive the modulator. These signals each produce at least one output beam as diffracted by the modulator body. These two beams are angularly and spatially separated. One of the sets of beams is incident upon a beam stop, and therefore is not used for writing. Only the other set of beams, driven by the other of the frequencies, performs the actual writing. The optical stop in addition to blocking one of the sets of diffracted beams also blocks the transmission of the zero order (undiffracted) beam. The sum of the load power of the signals at the two frequencies is kept approximately constant, thereby maintaining a constant thermal condition within the modulator.

Abstract: A multi-electrode cochlear implant is taught in which approximately twenty or more insulated metal wires are wound around a flexible tube. These wires are held in place with a further layer of dielectric insulating material. The insulation is selectively removed with a laser beam to form electrodes. Two or more layers or valences of wires can be used, with the inner layer of wires terminating distal to the outer layers to provide a stepwise approximation of the tapering of the scala tympani. A core of shape memory material may be introduced into the tube, so that the implant will retain an effective shape after implantation.

Abstract: Microelectrodes for use in stimulating and detecting activity in neurons of living organisms, and a method of manufacturing such microelectrodes. An electrically conductive electrode core member is sharpened and coated with a thin layer of a dielectric material. An extremely small area of the core at the sharpened point is exposed by ablating the dielectric material by the use of ultraviolet laser beam scanned over the material. Multiconductor microelectrodes include multiple fine wires which may be arranged in helical strands, optionally supported by a central core member of stiffer material. Multiple conductors may also be supported within a tubular support such as a hollow needle whose distal end is cut at a slant to expose the conductors, or in flat ribbon configuration with openings in dielectric material defining active electrode sites.

Abstract: A miniature, electrically-insulated multi-conductor electrical cable suitable for implantation in living bodies and readily connected to sensors or electrodes, and implantable microelectrodes attached to such cables. Individual electrical conductors are coated with at least one layer of, insulating material and stranded together, or optionally bound together by an additional layer of insulating material which is compatible with implantation in living bodies. The individual conductors are separated from one another in terminal portions of the cable and are held by a ribbonizing resin at a predetermined pitch to facilitate connection of each of the conductors. The terminal portions may define microelectrodes. Another microelectrode includes an electrically conductive electrode core member sharpened and coated with a thin layer of a dielectric material.

Abstract: Connectors for attachment to cables including a large number of very small flexible conductors (26) or coaxial conductor pairs (74). In a first embodiment very small contacts (36) are arrayed on a flat mating surface (28) of the connector body (22). Contacts (36) are raised slightly above the mating surface by plating conductive metal to form raised bumps (42) on one of a pair of connectors (14, 16). Insulated individual conductors (26) are placed through apertures (48) defined in a substrate acting as a template, and are fastened in place by potting material (50) before shaping the mating surface (28) of the connector body (22) or (24) is shaped. Pin and socket combinations (30, 32) are used to align mating connectors with each other.

Abstract: Connectors for attachment to cables including a large number of very small flexible conductors or conductor pairs, in which very small contacts are provided as an array exposed on a flat mating surface. Contacts may be raised slightly above the flat surface by plating conductive metal to form raised bumps on one of a pair of connectors. Individual conductors are placed through apertures defined in a substrate acting as a template, and are potted in place before shaping the mating surface of the connector. Contact bases to be plated may be defined precisely by photoresist lithography on a cover layer attached to the template substrate, and an elastomeric layer may be provided between the cover layer and the template substrate. Pin and socket combinations are used to align mating connectors with each other.