Patents by Inventor Jerry R. Bauer
Jerry R. Bauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7739097Abstract: A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces through the use of multiplexing.Type: GrantFiled: April 22, 2002Date of Patent: June 15, 2010Assignee: Quickturn Design Systems Inc.Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
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Patent number: 6732068Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.Type: GrantFiled: August 2, 2001Date of Patent: May 4, 2004Assignee: Quickturn Design Systems Inc.Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
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Publication number: 20030074178Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.Type: ApplicationFiled: April 22, 2002Publication date: April 17, 2003Applicant: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
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Publication number: 20020161568Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.Type: ApplicationFiled: August 2, 2001Publication date: October 31, 2002Applicant: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
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Patent number: 6377912Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.Type: GrantFiled: August 13, 1999Date of Patent: April 23, 2002Assignee: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
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Patent number: 5960191Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.Type: GrantFiled: May 30, 1997Date of Patent: September 28, 1999Assignee: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
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Patent number: 4716586Abstract: The addresses of firmward (ROM) being interrogated to ascertain data are continuously monitored. Selected key addresses are recognized by address detection means. Timing means is then actuated to count a preset number of address accesses, system clock cycles, or other suitable timing means. A substitute address is provided to the firmware when the timer counts down. If the incoming address is in the correct sequence then the substituted address will be the same as the incoming address and correct data will be provided by the ROM. Otherwise, incorrect data will be provided. Alternately, after countdown the incoming address can be compared with the expected incoming address. If the comparison indicates identity then the incoming address can be supplied to the firmware. Otherwise, an incorrect substitute address can be provided to the input of the firmware or incorrect substitute data can be provided on the output of the firmware.Type: GrantFiled: October 17, 1986Date of Patent: December 29, 1987Assignee: American Microsystems, Inc.Inventor: Jerry R. Bauer
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Patent number: 4698617Abstract: The present apparatus provides for the encoding of data carried on bus lines running between integrated circuits in order to protect the data carried upon those bus lines, with encoding and decoding circuits included for providing those functions in regard to the data on the bus lines.Type: GrantFiled: May 22, 1984Date of Patent: October 6, 1987Assignee: American Microsystems, Inc.Inventor: Jerry R. Bauer
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Patent number: 4673933Abstract: An encoding interface is provided between input data ports and strobe output ports of a (semiconductor integrated) circuit (chip) and an array of switches (40) is connected to a series of L input data lines and output lines (31-38), whereby the L lines can alternatively strobe the switch matrix to determine the (50) position of each switch. By having each line function either as an input line or an output line at a particular instant of time, the number of switches being served by a fixed number of total input and output lines is increased. For example, with eight total lines 28 switches are accommodated when the lines function either as input or output lines while when four separate lines are dedicated as input lines and four other lines dedicated as output lines only 16 switches are accommodated. In a further embodiment using two switches and a pair of oppositely disposed diodes at each cross point in the matrix the number of switches can be doubled (to 56 with eight dual input/output lines).Type: GrantFiled: November 14, 1983Date of Patent: June 16, 1987Assignee: American Microsystems, Inc.Inventor: Jerry R. Bauer