Abstract: A method of forming CMOS transistors with self-aligned field regions comprising the steps of providing on a silicon substrate first and second spaced apart areas for said CMOS transistors followed by forming a masking member on said substrate protecting the first of said areas and exposing the second. The second area is doped with a p-type material after which the size of the unmasked area is increased to that defining a p-well region to be formed therein surrounding said second area. Once the p-well region is formed, the same mask is employed to dope the p-well region with additional p-type material after which the CMOS transistors are fabricated in said first and second spaced apart areas.