Abstract: An aspect includes memory access optimization for an I/O adapter in a processor complex. A memory block distance is determined between the I/O adapter and a memory block location in the processor complex and determining one or more memory movement type criteria between the I/O adapter and the memory block location based on the memory block distance. A memory movement operation type is selected based on a memory movement process parameter and the one or more memory movement type criteria. A memory movement process is initiated between the I/O adapter and the memory block location using the memory movement operation type.

Abstract: An aspect includes memory access optimization in a processor complex. A non-limiting example includes determining one or more offload criteria for offloading memory movement in the processor complex. A memory movement process parameter corresponding to the one or more offload criteria is identified. Movement of a block of memory from a first block location at a first host to a second block location at a second host is scheduled as the memory movement process performed by an offload engine based on determining that the memory movement process parameter exceeds at least one of the offload criteria. The block of memory is moved from the first block location at the first host to the second block location at the second host as the memory movement process performed by the first host based on determining that the memory movement process parameter does not exceed at least one of the offload criteria.

Abstract: Ownership of a memory unit in a data processing system is tracked by assigning an identifier to each software component in the data processing system that can acquire ownership of the memory unit. An ownership variable is updated with the identifier of the software component that acquires ownership of the memory unit whenever the memory unit is acquired.

Abstract: An aspect includes memory access optimization for an I/O adapter in a processor complex. A memory block distance is determined between the I/O adapter and a memory block location in the processor complex and determining one or more memory movement type criteria between the I/O adapter and the memory block location based on the memory block distance. A memory movement operation type is selected based on a memory movement process parameter and the one or more memory movement type criteria. A memory movement process is initiated between the I/O adapter and the memory block location using the memory movement operation type.

Abstract: An aspect includes memory access optimization in a processor complex. A non-limiting example includes determining one or more offload criteria for offloading memory movement in the processor complex. A memory movement process parameter corresponding to the one or more offload criteria is identified. Movement of a block of memory from a first block location at a first host to a second block location at a second host is scheduled as the memory movement process performed by an offload engine based on determining that the memory movement process parameter exceeds at least one of the offload criteria. The block of memory is moved from the first block location at the first host to the second block location at the second host as the memory movement process performed by the first host based on determining that the memory movement process parameter does not exceed at least one of the offload criteria.

Abstract: A method, system and computer-usable medium are disclosed for performing a network traffic combination operation. With the network traffic combination operation, a plurality of input queues are defined by an operating system for an adapter based upon workload type (e.g., as determined by a transport layer). Additionally, the operating system defines each input queue to match a virtual memory architecture of the transport layer (e.g., one input queue is defined as 31 bit and other input queue is defined as 64 bit). When data is received off the wire as inbound data from a physical NIC, the network adapter associates the inbound data with the appropriate memory type. Thus, data copies are eliminated and memory consumption and associated storage management operations are reduced for the smaller bit architecture communications while allowing the operating system to continue executing in a larger bit architecture configuration.

Abstract: An aspect includes memory access optimization for an I/O adapter in a processor complex. A memory block distance is determined between the I/O adapter and a memory block location in the processor complex and determining one or more memory movement type criteria between the I/O adapter and the memory block location based on the memory block distance. A memory movement operation type is selected based on a memory movement process parameter and the one or more memory movement type criteria. A memory movement process is initiated between the I/O adapter and the memory block location using the memory movement operation type.

Abstract: A method, system and computer-usable medium are disclosed for performing a network traffic combination operation. With the network traffic combination operation, a plurality of input queues are defined by an operating system for an adapter based upon workload type (e.g., as determined by a transport layer). Additionally, the operating system defines each input queue to match a virtual memory architecture of the transport layer (e.g., one input queue is defined as 31 bit and other input queue is defined as 64 bit). When data is received off the wire as inbound data from a physical NIC, the network adapter associates the inbound data with the appropriate memory type. Thus, data copies are eliminated and memory consumption and associated storage management operations are reduced for the smaller bit architecture communications while allowing the operating system to continue executing in a larger bit architecture configuration.

Abstract: An aspect includes memory access optimization in a processor complex. A non-limiting example includes determining one or more offload criteria for offloading memory movement in the processor complex. A memory movement process parameter corresponding to the one or more offload criteria is identified. Movement of a block of memory from a first block location at a first host to a second block location at a second host is scheduled as the memory movement process performed by an offload engine based on determining that the memory movement process parameter exceeds at least one of the offload criteria. The block of memory is moved from the first block location at the first host to the second block location at the second host as the memory movement process performed by the first host based on determining that the memory movement process parameter does not exceed at least one of the offload criteria.

Abstract: A system for optimizing remote direct memory accesses (RDMA) is provided. The system includes a first computing device and a second computing device disposed in signal communication with the first computing device. The first and second computing devices are respectively configured to exchange RDMA credentials during a setup of a communication link between the first and second computing devices. The exchanged RDMA credentials include cache line size information of the first computing device by which a cache aligned RDMA write operation is executable on a cache of the first computing device in accordance with the cache line size information by the second computing device.

Abstract: An aspect includes memory access optimization for an I/O adapter in a processor complex. A memory block distance is determined between the I/O adapter and a memory block location in the processor complex and determining one or more memory movement type criteria between the I/O adapter and the memory block location based on the memory block distance. A memory movement operation type is selected based on a memory movement process parameter and the one or more memory movement type criteria. A memory movement process is initiated between the I/O adapter and the memory block location using the memory movement operation type.

Abstract: An aspect includes memory access optimization in a processor complex. A non-limiting example includes determining one or more offload criteria for offloading memory movement in the processor complex. A memory movement process parameter corresponding to the one or more offload criteria is identified. Movement of a block of memory from a first block location at a first host to a second block location at a second host is scheduled as the memory movement process performed by an offload engine based on determining that the memory movement process parameter exceeds at least one of the offload criteria. The block of memory is moved from the first block location at the first host to the second block location at the second host as the memory movement process performed by the first host based on determining that the memory movement process parameter does not exceed at least one of the offload criteria.

Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.

Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.

Abstract: Embodiments relate to protocol selection for transmission control protocol/internet protocol (TCP/IP). An aspect includes tracking connection data corresponding to a plurality of TCP/IP connections in a computer system. Another aspect includes determining, based on the tracked connection data, whether a particular connection of the plurality of TCP/IP connections is appropriate for sockets over remote direct memory access (RDMA) protocol. Another aspect includes, based on determining that the particular connection is appropriate for sockets over RDMA protocol, automatically enabling sockets over RDMA protocol for the connection. Yet another aspect includes, based on determining that the particular connection is not appropriate for sockets over RDMA protocol, automatically disabling sockets over RDMA protocol for the connection.

Abstract: Ownership of a memory unit in a data processing system is tracked by assigning an identifier to each software component in the data processing system that can acquire ownership of the memory unit. An ownership variable is updated with the identifier of the software component that acquires ownership of the memory unit whenever the memory unit is acquired.

Abstract: A system for optimizing remote direct memory accesses (RDMA) is provided. The system includes a first computing device and a second computing device disposed in signal communication with the first computing device. The first and second computing devices are respectively configured to exchange RDMA credentials during a setup of a communication link between the first and second computing devices. The exchanged RDMA credentials include cache line size information of the first computing device by which a cache aligned RDMA write operation is executable on a cache of the first computing device in accordance with the cache line size information by the second computing device.

Abstract: Ownership of a memory unit in a data processing system is tracked by assigning an identifier to each software component in the data processing system that can acquire ownership of the memory unit. An ownership variable is updated with the identifier of the software component that acquires ownership of the memory unit whenever the memory unit is acquired.

Abstract: A system for optimizing remote direct memory accesses (RDMA) is provided. The system includes a first computing device and a second computing device disposed in signal communication with the first computing device. The first and second computing devices are respectively configured to exchange RDMA credentials during a setup of a communication link between the first and second computing devices. The exchanged RDMA credentials include cache line size information of the first computing device by which a cache aligned RDMA write operation is executable on a cache of the first computing device in accordance with the cache line size information by the second computing device.

Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.