Abstract: An improved method and apparatus for decoding serial data uses a bit-wise synchronization technique in which a single bi-directional counter integrates the value of each successive bit to decode the bit state. The counter is sized relative to the receiver module oscillator frequency and the minimum data transmission speed to prevent overflow under worst case conditions, and the count is reset to one-half the maximum count at the beginning of each bit. During the bit period, oscillator clock pulses respectively increase or decrease the count when the bit value is above or below a threshold, and the bit value is determined in accordance with the most significant bit of the counter at the end of the respective bit period. Only a single counter is used to decode the data, and the data is substantially insensitive to noise because filtering can be used to reliably establish the state boundaries of the data bits.

Abstract: An integrated pulse-width modulation circuit with conditional temperature protection circuitry includes logic circuitry, a power output device, thermal shutdown circuitry to disable the power output device when the die temperature exceeds a predetermined limit, and a masking circuit that disables the thermal shutdown circuit during short term thermal increases such as those that occur when an inductive load turn off event takes place.