Abstract: Systems and methods for partial reconfiguration of reconfigurable application specific integrated circuit (ASIC) devices that may employ an interconnection template to allow partial reconfiguration (PR) blocks of an ASIC device to be selectively and dynamically interconnected and/or disconnected in standardized fashion from communication with a packet router within the same ASIC device.

Abstract: Systems and methods for partial reconfiguration of reconfigurable application specific integrated circuit (ASIC) devices that may employ an interconnection template to allow partial reconfiguration (PR) blocks of an ASIC device to be selectively and dynamically interconnected and/or disconnected in standardized fashion from communication with a packet router within the same ASIC device.

Abstract: Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Additionally, a communications infrastructure may be established across multiple circuit cards.

Abstract: Provided is a programmable matrix element or “PME” (which may be part of an ASIC central processing unit) operable to manipulate a data set of real and complex numbers derived from an input signal. Specific operations may include: addition, subtraction, multiplication, accumulation, storage and scaling. Each PME includes a plurality of multi-stage signal processing modules, which may be two-staged modules. Each state, in turn, includes: at least one data manipulation module for manipulating the input signal; a crosspoint switch for facilitating the receipt and parallel distribution of an input signal/manipulated output signal; and a programmable control module operable to support data manipulation by controlling manipulation functions, storing data and routing signals. A given crosspoint switch may be programmed to interconnect data manipulation modules in “datapipe” fashion, which is to say via a specified number of parallel data pathways.

Abstract: Provided is a digital signal processing device, specifically a modular application specific integrated circuit (“ASIC”), having a programmable crosspoint switch for facilitating data transfer and processing within the circuit. A programmable matrix element is operable to perform advanced matrix operations (arithmetic operations) according to user provided commands. The crosspoint switch interconnects the programmable matrix element with various other processing or conditioning modules (i.e. down conversion, filter, pulse processing and demodulation modules) to ensure parallel processing at System Clock rates. The ASIC, which is reconfigurable at a top-level according to user requirements, facilitates design changes and bench testing.

Abstract: Provided is a method and system for signal-driven recovery of a digital pulse stream. The method includes receiving initial parameters including the base characteristics of a pulse signal, the characteristics including the maximum pulse interval. An incoming analog signal is converted to a digital signal and sampled a predetermined number of times at intervals greater than the maximum pulse interval to record a set of minimum signal values and a set of maximum signal values. Each set is averaged to provide an average minimum value and an average maximum value. Based on these values at least one threshold value is then determined, and the digital pulse stream is identified based on the threshold values. The method is repetitive, continually re-determining the threshold values so as to adapt to changes in the incoming signal. A system for performing the method is also provided.

Abstract: Provided is a method and system for noise-driven recovery of a digital pulse stream. The method includes receiving initial parameters including the base characteristics of a pulse signal, the characteristics including the minimum pulse interval. An incoming analog signal is converted to a digital signal and sampled a predetermined number of times at intervals less than the minimum pulse interval to record a set of minimum signal values. The incoming signal is also sampled a predetermined number of times at intervals less than the minimum pulse interval to record a set of maximum signal values. At least the first greatest value from the set of maximum signal values is discarded. Each set is averaged to provide an average minimum value and an average maximum value. Based on these values at least one threshold value is then determined, and the digital pulse stream is identified based on the threshold values.

Abstract: Provided is a system and method for the development and distribution of a VHDL Intellectual Property (“IP”) Core. In particular, the system includes a module for regulating source control of core design files, a module for extracting or adding information to a file, and for controlling file release consistent with an IP Core Development Plan, and a module for ensuring the efficient integration of non-integral configuration design tools. A graphical user interface allows core designers to access and use system modules in an efficient and cost-effective manner. The reuse of IP core designs is facilitated by ensuring files are organized and controlled by file type, size, source control, etc., and by verifying that each file complies with the known or published IP Core Development Plan.

Abstract: Reconfigurable communications infrastructures may be implemented to interconnect ASIC devices (e.g., FPGAs) and other computing and input/output devices using high bandwidth interconnection mediums. The computing and input/output devices may be positioned in locations that are physically segregated from each other, and/or may be provided to project a reconfigurable network across a wide area. The reconfigurable communications infrastructures may be implemented to allow such computing and input/output devices to be used in different arrangements and applications, e.g., for use in any application where a large array of ASIC devices may be usefully employed such as supercomputing, etc.

Abstract: Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Additionally, a communications infrastructure may be established across multiple circuit cards.

Abstract: Systems and methods for providing a weighted overlap and add (WOLA) architecture and/or for providing polyphase WOLA FFT processing that may be employed, for example, for separation or channelization of closely-spaced frequencies of an input signal. A WOLA architecture that may be implemented as first-in-first-out (FIFO) cores in an FPGA or ASIC device. The FIFO cores may be pre-existing (e.g., provided as free FIFO cores in a commercial off the shelf (COTS) FPGA device) or may be custom-programmed into a custom ASIC device.

Abstract: Methods and systems for modeling concurrent behavior in a sequential programming environment using sequential-execution languages to describe and model multiple different processes which are running simultaneously.

Abstract: Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Additionally, a communications infrastructure may be established across multiple circuit cards.