Abstract: A method of fabrication and a structure for a low-loss optical device. The optical device structure includes a waveguide that is formed within a device layer of an SOI substrate. A cladding region is formed beneath the waveguide and a BOX layer of the SOI substrate. The cladding region may comprise an air cavity or a cavity that is filled or at least partially filled with a dielectric material. Because the cladding region is formed in the bottom side, it supplements the BOX layer cladding. Consequently, a thinner BOX layer may be used for both electronic and optical devices, which facilitates optoelectronic IC processing and design.

Abstract: A method of fabricating a Metal-Insulator-Metal (MIM) capacitor is presented. The method includes depositing a bottom plate of the MIM capacitor on a passivating dielectric layer which may be a pre-metal or post metal dielectric layer. A capacitor dielectric of the MIM capacitor is subsequently deposited on top of the bottom plate. The capacitor dielectric and the bottom plate both conform to the profile of the passivating dielectric layer. In addition, because the bottom plate is located on a dielectric, which is thermally stable and does not morph or change significantly with successive thermal processing, the capacitor dielectric does not have to be designed to compensate for topography changes due to such thermal processing.

Abstract: A process for forming a magnetoresistive bit and an interconnection to an underlying component forms a pattern in an amorphous dielectric overlying the magnetic materials. Portions of the magnetic materials are removed to form a bit having a smooth bit edge profile by ion milling. The bit has a bit end located over the underlying component. A second amorphous dielectric layer is deposited and etched at the bit end to form a via at the underlying component. Conventional first metal is used to form the interconnection.

Abstract: A method for fabricating polysilicon resistors of intermediate high value for use as cross-coupling or =ingle event upset (SEU) resistors in memory cells. A thin polysilicon film is implanted with arsenic ions to produce a predetermined resistivity. The thin film is then implanted with fluorine ions to stabilize the grain boundaries and thereby the barrier height. Reducing the variation in barrier height from run to run of wafers allows the fabrication of reproducible SEU resistors.

Abstract: A method of forming a self-aligned contact to a transistor component located on a semiconductor substrate comprising forming a transistor component opening in a masking layer overlying a semiconductor substrate and using epitaxial lateral overgrowth to form a self-aligned contact, the epitaxial overgrowth beginning in the masking layer opening at an upper surface of the semiconductor substrate and extending normal to and laterally over the masking layer surface.

Abstract: A method of forming a self-aligned contact to a transistor component located on a semiconductor substrate comprising forming a transistor component opening in a masking layer overlying a semiconductor substrate and using epitaxial lateral overgrowth to form a self-aligned contact, the epitaxial overgrowth beginning in the masking layer opening at an upper surface of the semiconductor substrate and extending normal to and laterally over the masking layer surface.