Abstract: Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.

Abstract: Integrated magnetics techniques for incorporating inductor, coupled inductor, and/or transformer functions of power electronics and high frequency circuits onto small, integrated structures, while maintaining a high quality factor and a high inductance density. The integrated magnetics techniques include incorporating magnetic vias into the inductive elements to form closed magnetic loops for reducing the reluctance to magnetic flux, while increasing the inductance of the inductive elements.

Abstract: A laminated transformer-type transmitter-receiver device for transmitting or delivering electrical signals and/or power. The laminated device can include two metal shielding layers disposed between transmit and receive windings, which, in turn, are disposed between two magnetic layers. The laminated device further includes a dielectric isolation layer disposed between the two metal shielding layers. In the laminated device, no (or very little) common mode capacitance is distributed within the dielectric isolation layer, and no (or very little) common mode or “leakage” current flows across the dielectric isolation layer. As a result, various adverse effects of the common mode capacitance and the leakage current during operation of the laminated device are avoided.

Abstract: Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.

Abstract: Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.

Abstract: A laminated transformer-type transmitter-receiver device for transmitting or delivering electrical signals and/or power. The laminated device can include two metal shielding layers disposed between transmit and receive windings, which, in turn, are disposed between two magnetic layers. The laminated device further includes a dielectric isolation layer disposed between the two metal shielding layers. In the laminated device, no (or very little) common mode capacitance is distributed within the dielectric isolation layer, and no (or very little) common mode or “leakage” current flows across the dielectric isolation layer. As a result, various adverse effects of the common mode capacitance and the leakage current during operation of the laminated device are avoided.

Abstract: Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.

Abstract: Integrated magnetics techniques for incorporating inductor, coupled inductor, and/or transformer functions of power electronics and high frequency circuits onto small, integrated structures, while maintaining a high quality factor and a high inductance density. The integrated magnetics techniques include incorporating magnetic vias into the inductive elements to form closed magnetic loops for reducing the reluctance to magnetic flux, while increasing the inductance of the inductive elements.

Abstract: Semiconductor chip laminates and inductive, capacitive, and electromagnetic shielding laminate structures that can be integrated together to form electronic circuits for use in systems and devices such as smartphones, tablet computers, notebook computers, wearable electronic devices, portable medical devices, servers, networking equipment, industrial equipment, etc. Fabrications of such integrated laminate structures can be modularized into four (4) types of laminates, namely, inductive laminates, capacitive laminates, electromagnetic shielding laminates, and semiconductor chip laminates, which can be vertically laminated together and/or integrated side-by-side with high density to produce the desired electronic circuits, systems, and devices.

Abstract: Systems and methods of charging battery power that can be selectively controlled by the overall voltage of a battery pack and specified voltages of battery cells within the battery pack, and that can selectively perform current-controlled and voltage-controlled battery charging (referred to herein as “adaptive battery cell charging”). The systems and methods employ a digital core for managing the charging of battery power provided by the battery pack. By using the overall voltage of the battery pack and specified voltages of battery cells to selectively control the charging of battery power, battery charging times can be reduced. By employing current/voltage sense amplifiers to monitor the battery pack voltage, the battery cell voltage(s), and a battery charging current, the effect of cable resistance to/from the battery pack can be reduced. By performing adaptive battery cell charging, battery charging times and battery stress can be reduced, while increasing battery charge/discharge life cycles.

Abstract: Systems and methods of implementing battery charging and energy saving systems in computers, computerized devices, medical devices, industrial devices, wearable devices, wireless charging devices, or any other suitable battery-operable devices. The systems and methods can control output voltages of battery charging systems during multiple charging/discharging periods, including a pre-charging period, a current-controlled charging period, a voltage-controlled charging period, a discharging period, as well as an additional period during which battery packs are removed or otherwise absent from the battery-operable devices or testing is being performed. The systems and methods also provide multiple energy saving modes for the battery-operable devices, allowing transitions between the respective energy saving modes both during operation of the battery-operable devices and during charging of the battery packs within the battery-operable devices.

Abstract: Semiconductor chip laminates and inductive, capacitive, and electromagnetic shielding laminate structures that can be integrated together to form electronic circuits for use in systems and devices such as smartphones, tablet computers, notebook computers, wearable electronic devices, portable medical devices, servers, networking equipment, industrial equipment, etc. Fabrications of such integrated laminate structures can be modularized into four (4) types of laminates, namely, inductive laminates, capacitive laminates, electromagnetic shielding laminates, and semiconductor chip laminates, which can be vertically laminated together and/or integrated side-by-side with high density to produce the desired electronic circuits, systems, and devices.

Abstract: Systems and methods of implementing battery charging and energy saving systems in computers, computerized devices, medical devices, industrial devices, wearable devices, wireless charging devices, or any other suitable battery-operable devices. The systems and methods can control output voltages of battery charging systems during multiple charging/discharging periods, including a pre-charging period, a current-controlled charging period, a voltage-controlled charging period, a discharging period, as well as an additional period during which battery packs are removed or otherwise absent from the battery-operable devices or testing is being performed. The systems and methods also provide multiple energy saving modes for the battery-operable devices, allowing transitions between the respective energy saving modes both during operation of the battery-operable devices and during charging of the battery packs within the battery-operable devices.

Abstract: Systems and methods of charging battery power that can be selectively controlled by the overall voltage of a battery pack and specified voltages of battery cells within the battery pack, and that can selectively perform current-controlled and voltage-controlled battery charging (referred to herein as “adaptive battery cell charging”). The systems and methods employ a digital core for managing the charging of battery power provided by the battery pack. By using the overall voltage of the battery pack and specified voltages of battery cells to selectively control the charging of battery power, battery charging times can be reduced. By employing current/voltage sense amplifiers to monitor the battery pack voltage, the battery cell voltage(s), and a battery charging current, the effect of cable resistance to/from the battery pack can be reduced. By performing adaptive battery cell charging, battery charging times and battery stress can be reduced, while increasing battery charge/discharge life cycles.

Abstract: A switching power supply controller has a nominal loop gain and transient loop gain that is only activated in response to an abrupt load change in one direction. The transient loop gain may be implemented with a series-connected diode and resistor combination arranged in a feedback configuration with an error amplifier. A large load change in one direction may swing the output of the error amplifier and forward bias the diode to create a non-linear gain change.

Abstract: A switching power supply controller has a nominal loop gain and transient loop gain that is only activated in response to an abrupt load change in one direction. The transient loop gain may be implemented with a series-connected diode and resistor combination arranged in a feedback configuration with an error amplifier. A large load change in one direction may swing the output of the error amplifier and forward bias the diode to create a non-linear gain change.