Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.

Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.

Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.

Abstract: There is disclosed a manipulator for positioning an interface of an automatic test system. In an embodiment, the manipulator includes a support device to support the interface. A base portion is in connection to the support device. The base portion includes a rotational adjustment mechanism for moving the support device about an axis of rotation. A planar adjustment mechanism moves the support device within a plane orthogonal to the axis of rotation. There is disclosed a method of positioning an interface unit of an automatic test system. In an embodiment, the method includes moving a support device supporting the interface unit a distance from a docking region of a material handling device; and rotating the support device about an axis of rotation passing through the interface unit. Other embodiments are also disclosed.

Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.

Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.

Abstract: A cartridge (10) includes a chuck plate (12) for receiving a wafer (74) and a probe plate (14) for establishing electrical contact with the wafer. In use, a mechanical connecting device (90) locks the chuck plate and the probe plate fixed relative to one another to maintain alignment of the wafer and the probe plate. Preferably, electrical contact with the wafer is established using a probe card (50) that is movably mounted to the probe plate by means of a plurality of leaf springs (52). The mechanical connecting device is preferably a kinematic coupling including a male connector (94) and first and second opposed jaws (122, 124). The cartridge can then be removed from the alignment device and placed in a burn-in or test chamber that does not itself require means for aligning the wafer or for providing a probing force.

Abstract: A burn-in and electrical test system (20) includes a temperature controlled zone (22) and a cool zone (24) separated by a transition zone 25. The temperature controlled zone (22) is configured to receive a plurality of wafer cartridges (26) and connect the cartridges (26) to test electronics (28) and power electronics (30), which are mounted in the cool zone (24). Each of the wafer cartridges (26) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics (28) consists of a pattern generator PCB (100) and a signal driver and fault analysis PCB (102) connected together by a parallel bus (104). The pattern generator PCB (100) and the fault analysis PCB (102) are connected to a rigid signal probe PCB (104) in cartridge (26) to provide a straight through signal path.

Abstract: This disclosure proposes an assembly structure for building probe cards to test square integrated circuit chips. The test probe card assembly structure has one or more wings located at 90.degree. angles to each other upon which probes are laid in a parallel manner for attachment to a probe card. This allows construction of the probe card so that probes touch contacts directly. The probe tips do not touch the contacts at an angle .theta., called the fan out angle. The probes also do not differ in their inclination angles .beta.. As a result, the force at which the many probe tips touch the contacts is relatively constant throughout. In addition, the probe tips are less likely to scrub past the surface of the contact onto the insulation surface of the chip and in doing so damage it. The test probe card assembly structure also contains an epoxy groove, which controls epoxy flow so that the position of the probes stays aligned in the correct plane. The epoxy groove also prevents variance in beam length.

Abstract: A method and device for accurately mounting a probe in a probe card and for maintaining correct location of the probe tip as the probe is used for electronic testing of an IC pad. A membrane having a slot is attached to a support structure of a probe card. The probe tip is inserted into the slot and the probe is affixed to the membrane at the edges of the slot using silicon rubber. The probe is then mounted in the support structure which has a groove for receiving the probe. A distal end of the probe is bonded to the walls of the groove so that the probe is free to move vertically in the groove, but constrained from moving laterally to prevent side-buckling. The membrane and silicon rubber hold the probe tip in proper location during thermal treating of the probe card assembly. Once mounted in the probe card by this method, the probe and probe tip will maintain proper location as they are used for electronic testing of an IC pad.