Patents by Inventor Jerzy Tyszer

Jerzy Tyszer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210156918
    Abstract: A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.
    Type: Application
    Filed: November 17, 2020
    Publication date: May 27, 2021
    Inventors: Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
  • Patent number: 10955460
    Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: March 23, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
  • Publication number: 20210018563
    Abstract: A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.
    Type: Application
    Filed: March 21, 2019
    Publication date: January 21, 2021
    Inventors: Janusz Rajski, Yu Huang, Sylwester Milewski, Jerzy Tyszer
  • Patent number: 10509072
    Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Sylwester Milewski, Nilanjan Mukherjee, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
  • Patent number: 10444282
    Abstract: Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: October 15, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Elham K. Moghaddam, Nilanjan Mukherjee, Jerzy Tyszer, Justyna Zawada
  • Patent number: 10379161
    Abstract: Various aspects of the present invention relate to scan chain stitching techniques for test-per-clock. With various implementations of the invention, a plurality of scan cell partitions are generated based on combinational paths between scan cells. Scan cells may be assigned to one or more pairs of scan cell partitions based on combinational paths between the scan cells. Each pair of the scan cell partitions comprises one stimuli partition and one compacting partition. Using the plurality of scan cell partitions generated, scan chains are formed based on at least information of combinational paths between scan cell partitions in the plurality of scan cell partitions. The formed scan chains are to be dynamically divided into three groups during a test, which are configured to operate in a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, respectively.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: August 13, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Patent number: 10361873
    Abstract: Various aspects of the disclosed technology relate to techniques of using control test points to enhance hardware security. The design-for-security circuitry reuses control test points, a part of design-for-test circuitry. The design-for-security circuitry comprises: identity verification circuitry; scrambler circuitry coupled; and test point circuitry. The test point circuitry comprises scan cells and logic gates The identify verification circuitry outputs an identity verification result to the scrambler circuitry to enable/disable control test points of the test point circuitry through the logic gates, and the scrambler circuitry outputs logic bits for loading the scan cells to activate/inactivate the control test points through the logic gates.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: July 23, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Nilanjan Mukherjee, Elham K. Moghaddam, Jerzy Tyszer, Justyna Zawada
  • Patent number: 10234506
    Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 19, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
  • Patent number: 10120029
    Abstract: Aspects of the disclosed technology relate to low power testing. A low power test circuit comprises a test stimulus source, a controller; and a grouping and selection unit. The grouping and selection unit has inputs coupled to the test stimulus source and the controller and has outputs coupled to a plurality of scan chains. The grouping and selection unit is configured to dynamically group scan chains in the plurality of scan chains into a plurality of scan chain groups and to selectively output either original test pattern values generated by the test stimulus source or a constant value to each scan chain group in the plurality of scan chain groups based on control signals received from the controller.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: November 6, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Sylwester Milewski, Grzegorz Mrugalski, Jerzy Tyszer
  • Patent number: 10120024
    Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 6, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
  • Publication number: 20180252768
    Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.
    Type: Application
    Filed: January 30, 2018
    Publication date: September 6, 2018
    Inventors: Janusz Rajski, Sylwester Milewski, Nilanjan Mukherjee, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
  • Publication number: 20180156867
    Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
    Type: Application
    Filed: October 2, 2017
    Publication date: June 7, 2018
    Applicant: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
  • Patent number: 9933485
    Abstract: Various aspects of the disclosed technology relate to deterministic built-in self-test. A deterministic built-in self-test system comprises: a decompressor configured at least to decompress one of compressed test patterns stored on chip for a predetermined number of times; and a controller configured at least to output a control signal that inverts outputs of the decompressor at one or more scan shift clock cycles based on control data stored on chip, enabling the system to output the predetermined number of test patterns based on the one of compressed test patterns, wherein the one or more scan shift clock cycles are different for each of the predetermined number of test patterns.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: April 3, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer
  • Publication number: 20180017622
    Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
    Type: Application
    Filed: May 30, 2017
    Publication date: January 18, 2018
    Applicant: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
  • Patent number: 9778316
    Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: October 3, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
  • Patent number: 9720041
    Abstract: Aspects of the invention relate to scan-based test architecture for interconnects in stacked designs. The disclosed scan-based test architecture comprises a scan chain. Scan cells on the scan chain are configured to receive data from, based on bits of a control signal, outputs of neighboring scan cells or outputs of mixing devices that combine data from through-silicon vias with data from the outputs of the neighboring scan cells. The scan-based test architecture can be used to identify single or multiple defective through-silicon vias.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: August 1, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer
  • Patent number: 9714981
    Abstract: Aspects of the invention relate to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. Every clock cycle, scan chains configured by a control signal to operate in a shifting-launching mode shift in test stimuli one bit and immediately applies the newly formed test pattern to the circuit-under-test; and scan chains configured by the control signal to operate in a capturing-compacting-shifting mode shift out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data. A large number of scan chains may be configured by the control signal to work in a mission mode. After a predetermined number of clock cycles, a different control signal may be applied to reconfigure and partition the scan chains for applying different test stimuli.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 25, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Patent number: 9664739
    Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 30, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rasjki, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
  • Publication number: 20170141930
    Abstract: Various aspects of the disclosed technology relate to techniques of using control test points to enhance hardware security. The design-for-security circuitry reuses control test points, a part of design-for-test circuitry. The design-for-security circuitry comprises: identity verification circuitry; scrambler circuitry coupled; and test point circuitry. The test point circuitry comprises scan cells and logic gates The identify verification circuitry outputs an identity verification result to the scrambler circuitry to enable/disable control test points of the test point circuitry through the logic gates, and the scrambler circuitry outputs logic bits for loading the scan cells to activate/inactivate the control test points through the logic gates.
    Type: Application
    Filed: November 16, 2016
    Publication date: May 18, 2017
    Inventors: Janusz Rajski, Nilanjan Mukherjee, Elham K. Moghaddam, Jerzy Tyszer, Justyna Zawada
  • Patent number: 9651622
    Abstract: Various aspects of the disclosed technology relate to techniques of creating test templates for test pattern generation. Residual test cubes for a plurality of faults are first generated based on a signal probability analysis of a circuit design. Test templates are then generated based on merging the residual test cubes. Finally, a plurality of test patterns and/or compressed test cubes are generated based on one of the test templates.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: May 16, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Amit Kumar, Mark A. Kassab, Elham Moghaddam, Nilanjan Mukherjee, Jerzy Tyszer, Chen Wang