Patents by Inventor Jesal Zevari

Jesal Zevari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Air-gap C4 fluidic I/O interconnects and methods of fabricating same
    Patent number: 8563365
    Abstract: An exemplary embodiment of the present invention provides a chip for use in fabricating a three-dimensional integrated circuit, the chip comprising a wafer, one or more metallic-filled, electrical vias, and one or more hollow, fluidic vias. The wafer can comprise a first surface and a second surface. The one or more metallic-filled, electrical vias can extend through the wafer. Each electrical via can be in electrical communication with an electrical interconnect proximate the first surface, providing electrical communication between chips in the integrated circuit. The one or more hollow, fluidic vias can extend through the wafer. Each fluidic via can be in fluid communication with a fluidic interconnect, providing fluid communication between adjacent chips in the integrated circuit. Each fluidic interconnect can comprise a first end proximate the first surface, a second end, and a cap proximate the second end, defining an air-filled space within the fluidic interconnect.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 22, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: Calvin Richard King, Jr., Jesal Zevari, James D. Meindl, Muhannad S. Bakir
  • AIR-GAP C4 FLUIDIC I/O INTERCONNECTS AND METHODS OF FABRICATING SAME
    Publication number: 20120228779
    Abstract: An exemplary embodiment of the present invention provides a chip for use in fabricating a three-dimensional integrated circuit, the chip comprising a wafer, one or more metallic-filled, electrical vias, and one or more hollow, fluidic vias. The wafer can comprise a first surface and a second surface. The one or more metallic-filled, electrical vias can extend through the wafer. Each electrical via can be in electrical communication with an electrical interconnect proximate the first surface, providing electrical communication between chips in the integrated circuit. The one or more hollow, fluidic vias can extend through the wafer. Each fluidic via can be in fluid communication with a fluidic interconnect, providing fluid communication between adjacent chips in the integrated circuit. Each fluidic interconnect can comprise a first end proximate the first surface, a second end, and a cap proximate the second end, defining an air-filled space within the fluidic interconnect.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 13, 2012
    Applicant: Georgia Tech Research Corporation
    Inventors: Calvin Richard King, JR., Jesal Zevari, James D. Meindl, Muhannad S. Bakir