Patents by Inventor Jeslin J. Wu
Jeslin J. Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12279431Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: May 17, 2023Date of Patent: April 15, 2025Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
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Publication number: 20240215246Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.Type: ApplicationFiled: March 5, 2024Publication date: June 27, 2024Inventors: Swapnil A. Lengade, Jeremy Adams, Naiming Liu, Jeslin J. Wu, Kadir Abdul, Carlo Mendoza Orofeo
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Publication number: 20240186267Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.Type: ApplicationFiled: February 15, 2024Publication date: June 6, 2024Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
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Patent number: 12004346Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.Type: GrantFiled: March 12, 2021Date of Patent: June 4, 2024Assignee: Micron Technology, Inc.Inventors: Swapnil Lengade, Jeremy Adams, Naiming Liu, Jeslin J. Wu, Kadir Abdul, Carlo Mendoza Orofeo
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Patent number: 11916024Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.Type: GrantFiled: September 14, 2021Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Rohit Kothari, Adam L Olson, John D. Hopkins, Jeslin J. Wu
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Publication number: 20230292510Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Applicant: Micron Technology, Inc.Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
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Patent number: 11706924Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: April 12, 2022Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
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Publication number: 20220293625Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.Type: ApplicationFiled: March 12, 2021Publication date: September 15, 2022Inventors: Swapnil Lengade, Jeremy Adams, Naiming Liu, Jeslin J. Wu, Kadir Abdul, Carlo Mendoza Orofeo
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Publication number: 20220238553Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: April 12, 2022Publication date: July 28, 2022Applicant: Micron Technology, Inc.Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunai Shrotri, Swapnil Lengade
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Patent number: 11329064Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: June 16, 2020Date of Patent: May 10, 2022Assignee: Micron Technology, Inc.Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
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Publication number: 20210407930Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.Type: ApplicationFiled: September 14, 2021Publication date: December 30, 2021Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
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Publication number: 20210391352Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: June 16, 2020Publication date: December 16, 2021Applicant: Micron Technology, Inc.Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
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Patent number: 11127691Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.Type: GrantFiled: December 28, 2018Date of Patent: September 21, 2021Assignee: Micron Technology, Inc.Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
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Publication number: 20200211981Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu