Patents by Inventor Jeslin J. Wu

Jeslin J. Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12279431
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: April 15, 2025
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
  • Publication number: 20240215246
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.
    Type: Application
    Filed: March 5, 2024
    Publication date: June 27, 2024
    Inventors: Swapnil A. Lengade, Jeremy Adams, Naiming Liu, Jeslin J. Wu, Kadir Abdul, Carlo Mendoza Orofeo
  • Publication number: 20240186267
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Application
    Filed: February 15, 2024
    Publication date: June 6, 2024
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
  • Patent number: 12004346
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: June 4, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Swapnil Lengade, Jeremy Adams, Naiming Liu, Jeslin J. Wu, Kadir Abdul, Carlo Mendoza Orofeo
  • Patent number: 11916024
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Adam L Olson, John D. Hopkins, Jeslin J. Wu
  • Publication number: 20230292510
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: May 17, 2023
    Publication date: September 14, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
  • Patent number: 11706924
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
  • Publication number: 20220293625
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Inventors: Swapnil Lengade, Jeremy Adams, Naiming Liu, Jeslin J. Wu, Kadir Abdul, Carlo Mendoza Orofeo
  • Publication number: 20220238553
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: April 12, 2022
    Publication date: July 28, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunai Shrotri, Swapnil Lengade
  • Patent number: 11329064
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
  • Publication number: 20210407930
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
  • Publication number: 20210391352
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: June 16, 2020
    Publication date: December 16, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
  • Patent number: 11127691
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
  • Publication number: 20200211981
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu