Abstract: Systems, apparatuses and methods may provide for technology that detects a plurality of sub-instruction requests from a first memory engine in a plurality of memory engines, wherein the plurality of sub-instruction requests are associated with a direct memory access (DMA) data type conversion request from a first pipeline, wherein each sub-instruction request corresponds to a data element in the DMA data type conversion request, and wherein the first memory engine is to correspond to the first pipeline, decodes the plurality of sub-instruction requests to identify one or more arguments, loads a source array from a dynamic random access memory (DRAM) in a plurality of DRAMs, wherein the operation engine is to correspond to the DRAM, and conducts a conversion of the source array from a first data type to a second data type in accordance with the one or more arguments.

Abstract: Systems, apparatuses and methods may provide for technology that includes a plurality of memory engines corresponding to a plurality of pipelines, wherein each memory engine in the plurality of memory engines is adjacent to a pipeline in the plurality of pipelines, and wherein a first memory engine is to request one or more direct memory access (DMA) operations associated with a first pipeline, and a plurality of operation engines corresponding to a plurality of dynamic random access memories (DRAMs), wherein each operation engine in the plurality of operation engines is adjacent to a DRAM in the plurality of DRAMs, and wherein one or more of the plurality of operation engines is to conduct the one or more DMA operations based on one or more bitmaps.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for performance of sparse matrix time dense matrix operations. Example instructions cause programmable circuitry to control execution of the sparse matrix times dense matrix operation using a sparse matrix and a dense matrix stored in memory, and transmit a plurality of instructions to execute the sparse matrix times dense matrix operation to DMA engine circuitry, the plurality of instructions to cause DMA engine circuitry to create an output matrix in the memory, the creation of the output matrix in the memory performed without the programmable circuitry computing the output matrix.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine refined context for bug detection. At least one non-transitory machine-readable medium includes instructions that, when executed, cause at least one processor to at least classify a node on a graph, the graph to represent a computer program, the node to contain partial bug context corresponding to the computer program; identify a location of a software bug in the computer program, the location based on the node; determine a static bug context of the software bug using the location of the software bug; determine a dynamic bug context of the software bug using the location of the software bug; and determine a refined bug context based on a merge of the static bug context and the dynamic bug context.

Abstract: Systems, apparatuses and methods may provide for technology that detects, by an operation engine, a plurality of sub-instruction requests from a first memory engine in a plurality of memory engines, wherein the plurality of sub-instruction requests are associated with a direct memory access (DMA) bitmap manipulation request from a first pipeline, wherein each sub-instruction request corresponds to a data element in the DMA bitmap manipulation request, and wherein the first memory engine is to correspond to the first pipeline. The technology also detects, by the operation engine, one or more arguments in the plurality of sub-instruction requests, sends, by the operation engine, one or more load requests to a DRAM in the plurality of DRAMs in accordance with the one or more arguments, and sends, by the operation engine, one or more store requests to the DRAM in accordance with the one or more arguments, wherein the operation engine is to correspond to the DRAM.

Abstract: Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.

Abstract: Methods, apparatus, systems, and articles of manufacture to determine execution cost are disclosed. An example apparatus includes memory; instructions included in the apparatus; and processor circuitry to execute the instruction to: cause a plurality of instructions corresponding to a mnemonic to be executed; determine an average execution cost of the plurality of instructions; determine a standard deviation of execution costs of the plurality of instructions; and generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

Abstract: Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.

Abstract: Methods, systems, and apparatus for automatic detection of software bugs are disclosed. An example apparatus includes a comparator to compare reference code to input code to detect a source code error in the input code; a graph generator to generate a graphical representation of the reference code or the input code, the graphical representation to identify non-overlapping code regions; and a root cause determiner to determine a root cause of the source code error in the input code, the root cause based on the non-overlapping code regions.

Abstract: Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to construct and compare program-derived semantic graphs comprising a leaf node creator to identify a first set of nodes within a parse tree, set a first abstraction level of a program-derived semantic graph (PSG) to contain the first set of nodes, an abstraction level determiner to access a second set of nodes, the second set of nodes to include the set of nodes in the PSG, create a third set of nodes, the third set of nodes to include the set of possible nodes at an abstraction level, determine whether the abstraction level is deterministic, a rule-based abstraction level creator to in response to determining the abstraction level is deterministic, construct the abstraction level, and a PSG comparator to access a first PSG and a second PSG, determine if the first PSG and the second PSG satisfy a similarity threshold.

Abstract: Disclosed examples to insert buffers in dataflow graphs include: a backedge filter to remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.

Abstract: Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.

Abstract: Disclosed examples to insert buffers in dataflow graphs include: a backedge filter to remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.