Abstract: Presented herein are facilities to assist in quality assurance (QA) testing of systems and equipment. Test data including results related to radiologic or diagnostic imaging performance of radiation therapy or diagnostic imaging equipment is obtained. Analysis of the test data is performed against maintained quality assurance specifications to obtain quality assurance results for the equipment. The obtained quality assurance results are presented to a user. Users may view trends and comparison in QA testing for the equipment and other equipment. Alerts about QA results may be provided and comments on QA results may be maintained. Collaboration between users to share information, test data, advice, and so on is facilitated.

Abstract: The invention is generally directed towards monitoring of a signal (m), such as a clock signal or a data signal, by sampling the signal to obtain a discrete sample representation of the signal and analyzing the sample representation. The idea according to the invention is to slide a sample window (sw) over the sampled signal and determine whether the samples currently within the window include a valid transition sequence. in the general case, the existence of a valid signal is confirmed as long as a valid transition sequence is present in at least one of a predetermined number of consecutive sample windows. in order to reduce the need for oversampling in high-frequency applications, the invention furthermore proposes a multi-phase sampling technique according to which a number of phase-shifted sample clocks (s1 to sn) are generated for the purpose of sampling the signal to be monitored. Higher-frequency oversampling is thus replaced by a higher resolution in the time domain.

Abstract: The invention represents a parallel and distributed approach to clock recovery based on multiple mutually phase shifted sample clock signals (åS) defining a set of orthogonal clock phases. The phase shifted clock signals are used for obtaining an input data sample representation (åU). Input data transition detection is accomplished by determining, for each one of the above clock phases, whether input data samples within a detection window associated with the respective clock phase include an input data transition vector (I). A corresponding clock selection control signal vector (I) is generated based on the input data transition vector (I) to determine a clock selection master. In order to dynamically extract an output clock signal, to control signal vector (I) is then logically combined with a representation (åS?), preferably a rotated version, of the sample clock vector (åS).

Abstract: The invention relates to a new family of differential oscillators based on oscillator amplifiers with local feedback forming respective local feedback systems, and at least one common link interconnecting the local feedback systems. Each branch of the differential oscillator includes an oscillator amplifier with a phase shifting and impedance transforming local feedback path from the output to the input of the amplifier to form a local feedback system. The differential oscillator also includes one or more common phase shifting links for interconnecting and cooperating with the local feedback systems to enable self-sustained differential oscillation. In differential mode operation, the electrical midpoint of the common phase shifting link(s) is virtually grounded and the local feedback systems of the two branches operate, together with the common phase shifting link(s), effectively in anti-phase with respect to each other as two separate oscillators.

Abstract: The present invention proposes a new way of improving the phase stability and frequency selectivity of a phase shift oscillator (100). By introducing a filter-order enhancing feedback loop (124) in association with a phase shift filter (122) in the oscillator, higher-order phase shift filtering can be achieved without using inductive elements as in conventional higher-order LC phase shift filters. This is a great advantage, since a high Q-value can be obtained without limited by the relatively high internal losses of inductive elements (L).

Abstract: The invention is generally directed towards monitoring of a signal (M), such as a clock signal or a data signal, by sampling the signal to obtain a discrete sample representation of the signal and analyzing the sample representation. The idea according to the invention is to slide a sample window (SW) over the sampled signal and determine whether the samples currently within the window include a valid transition sequence. In the general case, the existence of a valide signal is confirmed as long as a valid transition sequence is present in at least one of a predetermined number of consecutive sample windows. In order to reduce the need for oversampling in high-frequency applications, the invention furthermore proposes a multi-phase sampling technique according to which a number of phase-shifted sample clocks (S1 to SN) are generated for the purpose of sampling the signal to be monitored. Higher-frequency oversampling is thus replace by a higher resolution in the time domain.

Abstract: The invention relates to a new phase detector state machine having a reset state that is released only when both phase detector input signals (R, V) have a common predetermined signal state. In this way, phase inversion is effectively prevented. The complementary phase error is properly masked and the phase detector range is reduced to the interval—180°<&thgr;e<180°, while still maintaining the direction sensitivity. Phase errors &thgr;e larger than half a period are automatically discarded. Consequently, if the phase detector ends up in a state, for example due to reference clock loss, in which the phase error is larger than half a period, the phase detector will be shifted back to normal operation with a phase error less than half a period during the next consecutive phase comparison period. Naturally, this saves valuable time in the lock-acquisition procedure.

Abstract: The invention relates to a new family of differential oscillators based on oscillator amplifiers with local feedback forming respective local feedback systems, and at least one common link interconnecting the local feedback systems. Each branch of the differential oscillator includes an oscillator amplifier with a phase shifting and impedance transforming local feedback path from the output to the input of the amplifier to form a local feedback system. The differential oscillator also includes one or more common phase shifting links for interconnecting and cooperating with the local feedback systems to enable self-sustained differential oscillation. In differential mode operation, the electrical midpoint of the common phase shifting link(s) is virtually grounded and the local feedback systems of the two branches operate, together with the common phase shifting link(s), effectively in anti-phase with respect to each other as two separate oscillators.

Abstract: The present invention proposes a new way of improving the phase stability and frequency selectivity of a phase shift oscillator (100). By introducing a filter-order enhancing feedback loop (124) in association with a phase shift filter (122) in the oscillator, higher-order phase shift filtering can be achieved without using inductive elements as in conventional higher-order LC phase shift filters. This is a great advantage, since a high Q-value can be obtained without limited by the relatively high internal losses of inductive elements (L).

Abstract: The invention is generally directed towards monitoring of a signal (M), such as a clock signal or a data signal, by sampling the signal to obtain a discrete sample representation of the signal and analyzing the sample representation. The idea according to the invention is to slide a sample window (SW) over the sampled signal and determine whether the samples currently within the window include a valid transition sequence. In the general case, the existence of a valid signal is confirmed as long as a valid transition sequence is present in at least one of a predetermined number of consecutive sample windows. In order to reduce the need for oversampling in high-frequency applications, the invention furthermore proposes a multi-phase sampling technique according to which a number of phase-shifted sample clocks (S1 to SN) are generated for the purpose of sampling the signal to be monitored. Higher-frequency oversampling is thus replaced by a higher resolution in the time domain.

Abstract: The invention relates to a new phase detector state machine having a reset state that is released only when both phase detector input signals (R, V) have a common predetermined signal state. In this way, phase inversion is effectively prevented. The complementary phase erros is properly masked and the phase detector range is reduced to the interval −180°<&thgr;e<180°, while still maintaining the direction sensitivity. Phase errors &thgr;e larger than half a period are automatically discarded. Consequently, if the phase detector ends up in a state, for example due to reference clock loss, in which the phase error is larger than half a period, the phase detector will be shifted back to normal operation with a phase error less than half a period during the next consecutive phase comparison period. Naturally, this saves valuable time in the lock-acquisition procedure.

Abstract: The invention relates to reference handover in clock signal generation systems and similar applications. The idea according to the invention is to introduce a so-called “virtual” delay in the control loop of a PLL for the purpose of forcing the control loop to shift the phase of the PLL output clock signal, while still maintaining the mandatory phase lock condition of the PLL relative to a primary reference signal, towards a predetermined target phase relation with the primary reference signal. By utilizing a virtual delay, the problems associated with explicit delay elements such as passive or active delay lines are avoided, and a more robust and accurate clock phasing mechanism is obtained. Preferably, the virtual is introduced by superimposing an external phasing control signal in the control loop of the PLL on the output signal/input signal of a control loop element.

Abstract: The invention relates to reference handover in clock signal generation systems and similar applications. The idea according to the invention is to introduce a so-called “virtual” delay in the control loop of a PLL (10) for the purpose of forcing the control loop to shift the phase of the PLL output clock signal (VCOout), while still maintaining the mandatory phase lock condition of the PLL relative to a primary reference signal (MREF), towards a predetermined target phase relation with the primary reference signal. By utilizing a virtual delay (“&Dgr;T”), the problems associated with explicit delay elements such as passive or active delay lines are avoided, and a more robust and accurate clock phasing mechanism is obtained. Preferably, the virtual delay is introduced by superimposing an external phasing control signal in the control loop of the PLL (10) on the output signal/input signal of a control loop element.