Patents by Inventor Jesse C. Jones

Jesse C. Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11527484
    Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Jesse C. Jones, Gang Duan, Jason Gamba, Yosuke Kanaoka, Rahul N. Manepalli, Vishal Shajan
  • Publication number: 20210366835
    Abstract: Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated. substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 25, 2021
    Inventors: Srinivas Venkata Ramanuja Pietambaram, Rahul N. Manepalli, Praneeth Akkinepally, Jesse C. Jones, Yosuke Kanaoka, Dilan Seneviratne
  • Patent number: 11081448
    Abstract: Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that, provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli, Praneeth Akkinepally, Jesse C. Jones, Yosuke Kanaoka, Dilan Seneviratne
  • Patent number: 11062933
    Abstract: A die placement and coupling apparatus may include a die bonding attachment. The die placement and coupling apparatus may include a compliant head unit that may be adapted to optionally couple with a semiconductor die. The compliant head unit may include a die attach surface that may include a layer of compliant material. The layer of compliant material may be coupled to the compliant head unit. The die attach surface may be adapted to mate with the semiconductor die when the semiconductor die is coupled with the compliant head unit. The layer of compliant material may be adapted to yield in response to an applied force. The die placement and coupling apparatus may include a vacuum port in communication with the die attach surface. The port may be adapted to have a vacuum applied to the port, and the vacuum temporarily holds the semiconductor die to the die attach surface.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Jesse C. Jones, Gang Duan, Yosuke Kanaoka, Rahul N. Manepalli
  • Publication number: 20210043580
    Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Jesse C. JONES, Gang DUAN, Jason GAMBA, Yosuke KANAOKA, Rahul N. MANEPALLI, Vishal SHAJAN
  • Patent number: 10847471
    Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Jesse C. Jones, Gang Duan, Jason Gamba, Yosuke Kanaoka, Rahul N. Manepalli, Vishal Shajan
  • Publication number: 20200027775
    Abstract: A die placement and coupling apparatus may include a die bonding attachment. The die placement and coupling apparatus may include a compliant head unit that may be adapted to optionally couple with a semiconductor die. The compliant head unit may include a die attach surface that may include a layer of compliant material. The layer of compliant material may be coupled to the compliant head unit. The die attach surface may be adapted to mate with the semiconductor die when the semiconductor die is coupled with the compliant head unit. The layer of compliant material may be adapted to yield in response to an applied force. The die placement and coupling apparatus may include a vacuum port in communication with the die attach surface. The port may be adapted to have a vacuum applied to the port, and the vacuum temporarily holds the semiconductor die to the die attach surface.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 23, 2020
    Inventors: Jesse C. Jones, Gang Duan, Yosuke Kanaoka, Rahul N. Manepalli
  • Publication number: 20200027841
    Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 23, 2020
    Inventors: Jesse C. Jones, Gang Duan, Jason Gamba, Yosuke Kanaoka, Rahul N. Manepalli, Vishal Shajan
  • Publication number: 20190333861
    Abstract: Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 31, 2019
    Inventors: Srinivas V. Pietambaram, Rahul N. Manapalli, Praneeth Akkinepally, Jesse C. Jones, Yosuke Kanaoka, Dilan Seneviratne