Abstract: An automated system and method of determining power sequencing risks (e.g. power-up, power-down time sequences) for complex computer circuits with multiple independent power supplies. The system operates by logical consideration of the topological arrangement of MOSFETs and other devices in standard netlists. The system inspects the various devices and automatically traces DC circuit paths to DC power rails. The system then evaluates, as a type of logical existence proof, and on a per MOSFET device level, if due to assignment to different DC power levels, various factors, such as forward-biased diodes, floating MOSFET gate, and other risk factors could ever occur. The system generates comprehensive records of such risks and can output an overall analysis of a circuit reporting on both problematic power sequences, as well as circuit design factors that may be sub-optimal from a power sequence perspective.

Abstract: Method for automatically analyzing complex electronic circuit designs for generalized types of floating FET gate circuit design errors that encompass both standard floating gate issues and previously difficult-to-find high impedance situations. The invention views electronic circuits as comprising a large number of “circuit stacks”, each stack having a small number of electronic devices between a given power and ground rail within the circuit. The invention uses a computer processor and a recursion algorithm to automatically analyze circuit netlists, determine the different circuit stacks, stack input-output functions, and stack devices, and use an expression algorithm to determine a logical expression of the given stack's input-output function.

Abstract: An automated method of determining power sequencing risks (e.g. power-up, power-down time sequences) for complex computer circuits with multiple independent power supplies. The method operates by logical consideration of the topological arrangement of MOSFETs and other devices in standard netlists. The invention inspects the various devices and automatically traces DC circuit paths to DC power rails. The invention then evaluates, as a type of logical existence proof, and on a per MOSFET device level, if due to assignment to different DC power levels, various factors, such as forward-biased diodes, floating MOSFET gate, and other risk factors could ever occur. The method generates comprehensive records of such risks and can output an overall analysis of a circuit reporting on both problematic power sequences, as well as circuit design factors that may be sub-optimal from a power sequence perspective.

Abstract: An automated system and method of performing electronic design rule checking on the netlist of an integrated circuit composed of a plurality of subgraphs. The electronic design rule is embodied as a two part template with a target subgraph specification and a design rule compliance check specification. The target subgraph specification often is at least partially defined by an interactive visual programming section that allows the user to construct a graphic specification of the target netlist. The method first searches the netlist for target subgraphs that match the target subgraph specification, and the user can verify proper target selection. The method then performs rule checks on these search targets, and non compliant subnets identified. Flexibility is enhanced by use of search wildcards, attribute ranges, and various short user scripts which may contain various Boolean logical operations.

Abstract: Software method to identify presence of multiple digital drivers disposed in a manner that creates multiple conflicting current paths in complex electronic circuit designs. Digital drivers are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions that drive the digital driver's state. The previous level of predecessor circuit node states earlier in the circuit are checked to see if they simultaneously create pull up paths to power nets and pull down paths to ground nets, thus logically determining if a contention configuration is possible. This back-trace analysis is then repeated for the next previous level of predecessor circuit portions, further seeking logical contention issues within the expanding logic tree. This is continued until either no predecessor circuit portion that causes contention is found, or until a portion that does cause logical contention is found, in which case the contention digital drivers are reported.

Abstract: A logical and topological based software method of detecting level shifter circuits in complex integrated circuit designs. The method, which identifies level shifters by various design rules such as suitably connected PFET and NFET pairs in various circuit contexts, rather than prior art simulation methods, can identify and mark various devices and circuits as being part of a level shifter, and also place the identified level shifters within the context of the integrated circuit chip's various power domains. In some embodiments, the method, working with little or no a-priori information other than the integrated circuit's netlist computer file, can automatically trace power and signal lines, automatically determine power domains, and automatically flag when signal lines between different power domains are not adequately protected by level shifters.

Abstract: Software method to identify presence of multiple digital drivers disposed in a manner that creates multiple conflicting current paths in complex electronic circuit designs. Digital drivers are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions that drive the digital driver's state. The previous level of predecessor circuit node states earlier in the circuit are checked to see if they simultaneously create pull up paths to power nets and pull down paths to ground nets, thus logically determining if a contention configuration is possible. This back-trace analysis is then repeated for the next previous level of predecessor circuit portions, further seeking logical contention issues within the expanding logic tree. This is continued until either no predecessor circuit portion that causes contention is found, or until a portion that does cause logical contention is found, in which case the contention digital drivers are reported.

Abstract: A computer software implemented method of automatically determining adequacy of an integrated circuit electrical power distribution and signal protection schemes, based on netlist data, which does not rely on other a-priori data. The method determines which nets are power supply nets, their connectivity to different types of power supplies. The method automatically traverses the nested block structure of the circuit, ascending and descending in block hierarchy as needed, and automatically determines (often based on an inspection of the power needs of the individual block devices) the type of power supply needed to power that block, power supply adequacy, and adequate protection of signal interfaces to other blocks. The method can present the analysis in a high level report, such as a graphical map, that can make root cause sources of power and power related signal interface problems immediately evident, and which suppresses most irrelevant details.

Abstract: A computerized method of automatically identifying nets that are statistically likely to be power or ground nets in a complex integrated circuit design. The method, which does not require a-priori information, operates by determining electrical properties of each device or device terminal that is coupled to an analyzed net, and creating a mathematical description of overall electrical properties of these various devices. The method will then compare this mathematical description with at least various preset mathematical descriptions of power nets or a ground nets. If the mathematical description fits, the invention will at least provisionally determine that said analyzed net is a power net or a ground net. The invention may also determine likely voltages for these various power nets.

Abstract: Software method to identify which transistor gates float, and why, in complex, multi-transistor, electronic circuit designs. Transistor gates suspected of floating are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions which drive that suspect gate. The method checks if the previous level of predecessor circuit node states earlier in the circuit show up more than once with different values, thus indicating by logical conflict that a particular floating suspect gate does not float. It then repeats this back-trace analysis for the next previous level of predecessor circuit portions, further seeking logical conflicts within the expanding logic tree. This is continued until either no predecessor circuit portion that can cause the suspect gate to float is found, or until a portion that does cause the suspect gate to float is found, in which case the suspect gate is identified as a probable floating gate.

Abstract: An automated system and method of performing electronic design rule checking on the netlist of an integrated circuit composed of a plurality of subgraphs. The electronic design rule is embodied as a two part template with a target subgraph specification and a design rule compliance check specification. The target subgraph specification often is at least partially defined by an interactive visual programming section that allows the user to construct a graphic specification of the target netlist. The method first searches the netlist for target subgraphs that match the target subgraph specification, and the user can verify proper target selection. The method then performs rule checks on these search targets, and non compliant subnets identified. Flexibility is enhanced by use of search wildcards, attribute ranges, and various short user scripts which may contain various Boolean logical operations.

Abstract: A computer software implemented method of automatically determining adequacy of an integrated circuit electrical power distribution and signal protection schemes, based on netlist data, which does not rely on other a-priori data. The method determines which nets are power supply nets, their connectivity to different types of power supplies. The method automatically traverses the nested block structure of the circuit, ascending and descending in block hierarchy as needed, and automatically determines (often based on an inspection of the power needs of the individual block devices) the type of power supply needed to power that block, power supply adequacy, and adequate protection of signal interfaces to other blocks. The method can present the analysis in a high level report, such as a graphical map, that can make root cause sources of power and power related signal interface problems immediately evident, and which suppresses most irrelevant details.

Abstract: A logical and topological based software method of detecting level shifter circuits in complex integrated circuit designs. The method, which identifies level shifters by various design rules such as suitably connected PFET and NFET pairs in various circuit contexts, rather than prior art simulation methods, can identify and mark various devices and circuits as being part of a level shifter, and also place the identified level shifters within the context of the integrated circuit chip's various power domains. In some embodiments, the method, working with little or no a-priori information other than the integrated circuit's netlist computer file, can automatically trace power and signal lines, automatically determine power domains, and automatically flag when signal lines between different power domains are not adequately protected by level shifters.

Abstract: Systems and methods for deriving a net equation representing a net state of an analog circuit net, wherein the net equation is derived from at least one other net state, determining a truthfulness of the net equation, reporting the truthfulness.

Abstract: A computerized method of automatically identifying nets that are statistically likely to be power or ground nets in a complex integrated circuit design. The method, which does not require a-priori information, operates by determining the electrical properties of each device or device terminal that is coupled to the analyzed net, and creating an overall mathematical description of the overall electrical properties of these various devices. The method will then compare this mathematical description with at least various preset mathematical descriptions of power nets or a ground nets. If the overall mathematical description fits, the invention will at least provisionally determine that this particular analyzed net is a power net or a ground net. The invention may also determine likely voltages for these various power nets.

Abstract: Software method to identify which transistor gates float, and why, in complex, multi-transistor, electronic circuit designs. Transistor gates suspected of floating are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions which drive that suspect gate. The method checks if the previous level of predecessor circuit node states earlier in the circuit show up more than once with different values, thus indicating by logical conflict that a particular floating suspect gate does not float. It then repeats this back-trace analysis for the next previous level of predecessor circuit portions, further seeking logical conflicts within the expanding logic tree. This is continued until either no predecessor circuit portion that can cause the suspect gate to float is found, or until a portion that does cause the suspect gate to float is found, in which case the suspect gate is identified as a probable floating gate.

Abstract: Systems and methods for deriving a net equation representing a net state of an analog circuit net, wherein the net equation is derived from at least one other net state, determining a truthfulness of the net equation, reporting the truthfulness.