Patents by Inventor Jesse Conrad

Jesse Conrad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120266121
    Abstract: A computer software implemented method of automatically determining adequacy of an integrated circuit electrical power distribution and signal protection schemes, based on netlist data, which does not rely on other a-priori data. The method determines which nets are power supply nets, their connectivity to different types of power supplies. The method automatically traverses the nested block structure of the circuit, ascending and descending in block hierarchy as needed, and automatically determines (often based on an inspection of the power needs of the individual block devices) the type of power supply needed to power that block, power supply adequacy, and adequate protection of signal interfaces to other blocks. The method can present the analysis in a high level report, such as a graphical map, that can make root cause sources of power and power related signal interface problems immediately evident, and which suppresses most irrelevant details.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 18, 2012
    Inventor: Jesse Conrad Newcomb
  • Publication number: 20120266122
    Abstract: A logical and topological based software method of detecting level shifter circuits in complex integrated circuit designs. The method, which identifies level shifters by various design rules such as suitably connected PFET and NFET pairs in various circuit contexts, rather than prior art simulation methods, can identify and mark various devices and circuits as being part of a level shifter, and also place the identified level shifters within the context of the integrated circuit chip's various power domains. In some embodiments, the method, working with little or no a-priori information other than the integrated circuit's netlist computer file, can automatically trace power and signal lines, automatically determine power domains, and automatically flag when signal lines between different power domains are not adequately protected by level shifters.
    Type: Application
    Filed: May 30, 2012
    Publication date: October 18, 2012
    Applicant: INSIGHT EDA, INC.
    Inventors: Jesse Conrad Newcomb, Govinda Keshavdas
  • Patent number: 8225251
    Abstract: Systems and methods for deriving a net equation representing a net state of an analog circuit net, wherein the net equation is derived from at least one other net state, determining a truthfulness of the net equation, reporting the truthfulness.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: July 17, 2012
    Inventor: Jesse Conrad Newcomb
  • Publication number: 20120151427
    Abstract: A computerized method of automatically identifying nets that are statistically likely to be power or ground nets in a complex integrated circuit design. The method, which does not require a-priori information, operates by determining the electrical properties of each device or device terminal that is coupled to the analyzed net, and creating an overall mathematical description of the overall electrical properties of these various devices. The method will then compare this mathematical description with at least various preset mathematical descriptions of power nets or a ground nets. If the overall mathematical description fits, the invention will at least provisionally determine that this particular analyzed net is a power net or a ground net. The invention may also determine likely voltages for these various power nets.
    Type: Application
    Filed: February 21, 2012
    Publication date: June 14, 2012
    Inventor: Jesse Conrad Newcomb
  • Publication number: 20120110528
    Abstract: Software method to identify which transistor gates float, and why, in complex, multi-transistor, electronic circuit designs. Transistor gates suspected of floating are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions which drive that suspect gate. The method checks if the previous level of predecessor circuit node states earlier in the circuit show up more than once with different values, thus indicating by logical conflict that a particular floating suspect gate does not float. It then repeats this back-trace analysis for the next previous level of predecessor circuit portions, further seeking logical conflicts within the expanding logic tree. This is continued until either no predecessor circuit portion that can cause the suspect gate to float is found, or until a portion that does cause the suspect gate to float is found, in which case the suspect gate is identified as a probable floating gate.
    Type: Application
    Filed: January 8, 2012
    Publication date: May 3, 2012
    Inventor: Jesse Conrad Newcomb
  • Publication number: 20100306608
    Abstract: Systems and methods for deriving a net equation representing a net state of an analog circuit net, wherein the net equation is derived from at least one other net state, determining a truthfulness of the net equation, reporting the truthfulness.
    Type: Application
    Filed: January 26, 2010
    Publication date: December 2, 2010
    Applicant: INSIGHT EDA INC
    Inventor: Jesse Conrad Newcomb