Patents by Inventor Jesse D. Hall

Jesse D. Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8860743
    Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: October 14, 2014
    Assignee: Nvidia Corporation
    Inventors: Andrew Tao, Jerome F. Duluk, Jr., Jesse D. Hall, Henry Moreton
  • Patent number: 8681169
    Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: March 25, 2014
    Assignee: Nvidia Corporation
    Inventors: Jesse D. Hall, Jerome F. Duluk, Jr., Andrew Tao, Henry Moreton
  • Publication number: 20110157205
    Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Applicant: NVIDIA CORPORATION
    Inventors: Andrew Tao, Jerome F. Duluk, JR., Jesse D. Hall, Henry Moreton
  • Publication number: 20110157207
    Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Applicant: NVIDIA CORPORATION
    Inventors: Jesse D. Hall, Jerome F. Duluk, JR., Andrew Tao, Henry Moreton
  • Patent number: 7167176
    Abstract: Real-time processing includes per-point transfer matrices forming a high-dimensional surface signal that is compressed using clustered principal component analysis (CPCA). CPCA partitions multiple samples into fewer clusters, each cluster approximating the signal as an affine subspace. Further, source radiance is input to a processor, which approximates source radiance using spherical harmonic basis to produce a set of source radiance coefficients. A graphics processing unit (GPU) processes the source radiance coefficients through the transfer matrix model for each cluster. The result of such processing is the exit radiance, which parameterizes the radiance leaving the surface of the object at each point, thus producing the shading for each point of the virtual object in real time.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: January 23, 2007
    Assignee: Microsoft Corporation
    Inventors: Peter-Pike Sloan, John Michael Snyder, Jesse D. Hall