Patents by Inventor Jesse E. Galloway

Jesse E. Galloway has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240118061
    Abstract: Shaped charge devices, systems, and related methods of use. A housing sheet is configurable to form at least part of a shaped charge enclosure enclosing a shaped charge and biasing an explosion in a desired direction. The housing sheet can include one or more incisions in at least one surface thereof. The housing sheet can have at least one connection mechanism integrally formed therein, and the housing sheet can be configurable to form a plurality of sizes of shaped charge housing portions. The housing sheet can also provide for forming a plurality of dimensions of the shaped charge enclosure.
    Type: Application
    Filed: May 12, 2023
    Publication date: April 11, 2024
    Inventors: Kevin C. Galloway, Kelsay E. Neely, Aimee J. Valles, Robert J. Clark, Jesse L. Frederick
  • Patent number: 9892990
    Abstract: Semiconductor package lid thermal interface material standoffs are disclosed and may include a substrate, a semiconductor die bonded to the substrate, a package lid bonded to the substrate and the semiconductor die thermal interface material in contact the semiconductor die, and standoffs that define a distance between the package lid and the substrate. The package lid may comprise thermal conducting material. The standoff may be within a portion of the thermal interface material. The package lid may provide a hermetic seal with the substrate. A passive device may be bonded to the substrate and covered by the package lid. A standoffs may also be formed on portions of the lid that are not in contact with the substrate. The standoff may be formed on four edges of the package lid. The standoff may comprise structures pressed into the lid.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: February 13, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jesse E. Galloway, Paul Mescher
  • Patent number: 8217507
    Abstract: A semiconductor package which is structured to allow for the edge mounting thereof in a vertical mount orientation. The semiconductor package comprises a flexible substrate or “flex circuit.” The flexible substrate includes a conductive pattern disposed on a first surface thereof, and a plurality of conductive pads or terminals disposed on a second surface thereof which is disposed in opposed relation to the first surface. Mounted to the first surface of the flexible substrate are one or more electronic components such as semiconductor dies. The semiconductor die(s) is/are electrically connected to the conductive pattern, and thereafter covered or encapsulated by a package body applied to a portion of the first surface of the flexible substrate. That portion of the flexible substrate including the conductive pads or terminals formed on the second surface thereof is thereafter folded and adhered to a portion of the package body through the use of a suitable adhesive.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: July 10, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Jesse E. Galloway, Bob-Shih Wei Kuo, Ahmer Syed
  • Patent number: 7906845
    Abstract: A semiconductor device has a substrate having a top and bottom surface and a plurality of metal layers. A first die is electrically coupled to the top surface of the substrate. A lid member is attached to a top surface of the die and to the top surface of the substrate. A layering is formed on portions of a top surface of the lid member. The layering will have a different coefficient of thermal expansion (CTE) than the lid member.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: March 15, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Jesse E. Galloway, Sasanka Laxmi Narasimha Kanuparthi
  • Patent number: 6444563
    Abstract: A ball grid array (BGA) or chips scale package (CSP) integrated circuit (IC) (20) is manufactured by first identifying the most unreliable solder ball joints in the IC. These worst case joints, or joints in the vicinity of the worst case joints, are changed in pad dimension and exposed to more ball/bump conductive material than the other more robust joints (14) in the IC (20) to create a ball (24) on a larger pad (22) that is larger than the normal sized ball (14). The larger balls (24) are formed by placing multiple smaller balls (14) together on a single pad (22) to form one larger ball (24) during a reflow operation. The larger ball (24) improves the overall IC reliability by improving the reliability of the weakest joints in the IC design. In addition, the standoff of both the larger balls (24) and the smaller balls (14) are engineered to be substantially equal.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: September 3, 2002
    Assignee: Motorlla, Inc.
    Inventors: Scott G. Potter, Joseph Guy Gillette, Jesse E. Galloway, Zane Eric Johnson, Pradeep Lall
  • Publication number: 20020100955
    Abstract: A ball grid array (BGA) or chips scale package (CSP) integrated circuit (IC) (20) is manufactured by first identifying the most unreliable solder ball joints in the IC. These worst case joints, or joints in the vicinity of the worst case joints, are changed in pad dimension and exposed to more ball/bump conductive material than the other more robust joints (14) in the IC (20) to create a ball (24) on a larger pad (22) that is larger than the normal sized ball (14). The larger balls (24) are formed by placing multiple smaller balls (14) together on a single pad (22) to form one larger ball (24) during a reflow operation. The larger ball (24) improves the overall IC reliability by improving the reliability of the weakest joints in the IC design. In addition, the standoff of both the larger balls (24) and the smaller balls (14) are engineered to be substantially equal.
    Type: Application
    Filed: February 22, 1999
    Publication date: August 1, 2002
    Inventors: SCOTT G. POTTER, JOSEPH GUY GILLETTE, JESSE E. GALLOWAY, ZANE ERIC JOHNSON, PRADEEP LALL
  • Patent number: 5689403
    Abstract: An intercooled electronic device, includes a thermally conductive chassis (110), a substrate (120) mounted onto the chassis (110), a housing (104) formed around the chassis (110), and a cooling fan (130) mounted internally within the housing (104). The substrate (120) carries electrical circuitry including at least one heat-generating component (122) which is thermally coupled to the chassis (110). The cooling fan (130) is oriented to direct air across the chassis (110).
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: November 18, 1997
    Assignee: Motorola, Inc.
    Inventors: William H. Robertson, Jr., David E. Reiff, Richard A. Ceraldi, Sivakumar Muthuswamy, Craig K. Gygi, Jesse E. Galloway, Andrzej T. Guzik, MacWilliam Branan