Abstract: The present system may be utilized to minimize access performance penalties in memory subsystems which utilize redundant arrays of disk memory devices. Redundant arrays of disk memory devices provide levels of reliability which are not available with single storage devices; however, the redundancy carries with it an access performance degradation due to the requirement that such systems write data segments and parity elements to the array each time an application updates data within the system. A large nonvolatile cache is therefore provided in association with a redundant array of disk memory devices. Each time a data segment is written or read the data segment is staged from the array to the nonvolatile cache, if the data segment is not already within the cache. Additionally, if the operation is an update, a parity element associated with the data segment to be updated is also staged to the cache with the existing data segment content.

Abstract: An improved input/output subsystem allowing data transfers between the input/output subsystem and an input/output controller along a subsystem input/output bus to occur at a data transfer rate established by the transfer rate of the processor bus connected between the input/output controller and the central processing unit. Data is transferred from an electronic memory within the input/output subsystem to data buffers within the input/output controller via a direct memory access.

Abstract: In a data processing system communicating with disc drives via a disk channel, a disc cache subsystem coupled between the outboard side of the channel and the disc drives. The disc cache subsystem includes a plural-level cache memory comprised of a first memory and a second memory, wherein the first memory serves as input/output storage for the second memory. Provision is also made for controlling which of a plurality of disc drives is to be subject to caching by controlling which drives are to be bypassed.

Abstract: An improved input/output subsystem allowing data transfers between the input/output subsystem and an input/output controller along a subsystem input/output bus to occur at a data transfer rate established by the transfer rate of the processor bus connected between the input/output controller and the central processing unit. Data is transferred from an electronic memory within the input/output subsystem to data buffers within the input/output controller via a direct memory access.

Abstract: Write precompensation data is recorded on a disk of a magnetic disk drive indicating the write compensation to be provided for each of a plurality of head/media combination which may have relatively wide variations in performance characteristics. Apparatus is provided for transferring and storing this write precompensation data in the disk controller at start-up and for accessing this stored data during each write operation to provide a "tailored" write precompensation for the particular head/media combination to be employed for the writing operation.

Abstract: An improved input/output subsystem allowing data transfers between the input/output subsystem and an input/output controller along a subsystem input/output bus to occur at a data transfer rate established by the transfer rate of the processor bus connected between the input/output controller and the central processing unit. Data is transferred from an electronic memory within the input/output subsystem to data buffers within the input/output controller via a direct memory access.